Path: blob/master/Documentation/devicetree/bindings/display/brcm,bcm2835-dsi0.yaml
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# SPDX-License-Identifier: GPL-2.01%YAML 1.22---3$id: http://devicetree.org/schemas/display/brcm,bcm2835-dsi0.yaml#4$schema: http://devicetree.org/meta-schemas/core.yaml#56title: Broadcom VC4 (VideoCore4) DSI Controller78maintainers:9- Eric Anholt <eric@anholt.net>1011allOf:12- $ref: dsi-controller.yaml#1314properties:15"#clock-cells":16const: 11718compatible:19enum:20- brcm,bcm2711-dsi121- brcm,bcm2835-dsi022- brcm,bcm2835-dsi12324reg:25maxItems: 12627clocks:28items:29- description: The DSI PLL clock feeding the DSI analog PHY30- description: The DSI ESC clock31- description: The DSI pixel clock3233clock-names:34items:35- const: phy36- const: escape37- const: pixel3839clock-output-names: true40# FIXME: The meta-schemas don't seem to allow it for now41# items:42# - description: The DSI byte clock for the PHY43# - description: The DSI DDR2 clock44# - description: The DSI DDR clock4546interrupts:47maxItems: 14849power-domains:50maxItems: 15152required:53- "#clock-cells"54- compatible55- reg56- clocks57- clock-names58- clock-output-names59- interrupts6061unevaluatedProperties: false6263examples:64- |65#include <dt-bindings/clock/bcm2835.h>6667dsi1: dsi@7e700000 {68compatible = "brcm,bcm2835-dsi1";69reg = <0x7e700000 0x8c>;70interrupts = <2 12>;71#address-cells = <1>;72#size-cells = <0>;73#clock-cells = <1>;7475clocks = <&clocks BCM2835_PLLD_DSI1>,76<&clocks BCM2835_CLOCK_DSI1E>,77<&clocks BCM2835_CLOCK_DSI1P>;78clock-names = "phy", "escape", "pixel";7980clock-output-names = "dsi1_byte", "dsi1_ddr2", "dsi1_ddr";8182};8384...858687