Path: blob/master/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)1%YAML 1.22---3$id: http://devicetree.org/schemas/display/bridge/cdns,mhdp8546.yaml#4$schema: http://devicetree.org/meta-schemas/core.yaml#56title: Cadence MHDP8546 bridge78maintainers:9- Swapnil Jakhade <sjakhade@cadence.com>10- Yuti Amonkar <yamonkar@cadence.com>1112properties:13compatible:14enum:15- cdns,mhdp854616- ti,j721e-mhdp85461718reg:19minItems: 120items:21- description:22Register block of mhdptx apb registers up to PHY mapped area (AUX_CONFIG_P).23The AUX and PMA registers are not part of this range, they are instead24included in the associated PHY.25- description:26Register block for DSS_EDP0_INTG_CFG_VP registers in case of TI J7 SoCs.27- description:28Register block of mhdptx sapb registers.2930reg-names:31minItems: 132items:33- const: mhdptx34- const: j721e-intg35- const: mhdptx-sapb3637clocks:38maxItems: 139description:40DP bridge clock, used by the IP to know how to translate a number of41clock cycles into a time (which is used to comply with DP standard timings42and delays).4344phys:45maxItems: 146description:47phandle to the DisplayPort PHY.4849phy-names:50items:51- const: dpphy5253power-domains:54maxItems: 15556interrupts:57maxItems: 15859ports:60$ref: /schemas/graph.yaml#/properties/ports6162properties:63port@0:64$ref: /schemas/graph.yaml#/properties/port65description:66First input port representing the DP bridge input.6768port@1:69$ref: /schemas/graph.yaml#/properties/port70description:71Second input port representing the DP bridge input.7273port@2:74$ref: /schemas/graph.yaml#/properties/port75description:76Third input port representing the DP bridge input.7778port@3:79$ref: /schemas/graph.yaml#/properties/port80description:81Fourth input port representing the DP bridge input.8283port@4:84$ref: /schemas/graph.yaml#/properties/port85description:86Output port representing the DP bridge output.8788required:89- port@090- port@49192allOf:93- if:94properties:95compatible:96contains:97const: ti,j721e-mhdp854698then:99properties:100reg:101minItems: 2102maxItems: 3103reg-names:104minItems: 2105maxItems: 3106else:107properties:108reg:109minItems: 1110maxItems: 2111reg-names:112minItems: 1113maxItems: 2114115required:116- compatible117- clocks118- reg119- reg-names120- phys121- phy-names122- interrupts123- ports124125additionalProperties: false126127examples:128- |129#include <dt-bindings/interrupt-controller/arm-gic.h>130bus {131#address-cells = <2>;132#size-cells = <2>;133134mhdp: dp-bridge@f0fb000000 {135compatible = "cdns,mhdp8546";136reg = <0xf0 0xfb000000 0x0 0x1000000>;137reg-names = "mhdptx";138clocks = <&mhdp_clock>;139phys = <&dp_phy>;140phy-names = "dpphy";141interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>;142143ports {144#address-cells = <1>;145#size-cells = <0>;146147port@0 {148reg = <0>;149dp_bridge_input: endpoint {150remote-endpoint = <&xxx_dpi_output>;151};152};153154port@4 {155reg = <4>;156dp_bridge_output: endpoint {157remote-endpoint = <&xxx_dp_connector_input>;158};159};160};161};162};163...164165166