Path: blob/master/Documentation/devicetree/bindings/display/bridge/chipone,icn6211.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)1%YAML 1.22---3$id: http://devicetree.org/schemas/display/bridge/chipone,icn6211.yaml#4$schema: http://devicetree.org/meta-schemas/core.yaml#56title: Chipone ICN6211 MIPI-DSI to RGB Converter bridge78maintainers:9- Jagan Teki <jagan@amarulasolutions.com>1011description: |12ICN6211 is MIPI-DSI to RGB Converter bridge from chipone.1314It has a flexible configuration of MIPI DSI signal input and15produce RGB565, RGB666, RGB888 output format.1617properties:18compatible:19enum:20- chipone,icn62112122reg:23maxItems: 124description: virtual channel number of a DSI peripheral2526clock-names:27const: refclk2829clocks:30maxItems: 131description: |32Optional external clock connected to REF_CLK input.33The clock rate must be in 10..154 MHz range.3435enable-gpios:36description: Bridge EN pin, chip is reset when EN is low.3738vdd1-supply:39description: A 1.8V/2.5V/3.3V supply that power the MIPI RX.4041vdd2-supply:42description: A 1.8V/2.5V/3.3V supply that power the PLL.4344vdd3-supply:45description: A 1.8V/2.5V/3.3V supply that power the RGB output.4647ports:48$ref: /schemas/graph.yaml#/properties/ports4950properties:51port@0:52$ref: /schemas/graph.yaml#/$defs/port-base53unevaluatedProperties: false54description:55Video port for MIPI DSI input5657properties:58endpoint:59$ref: /schemas/media/video-interfaces.yaml#60unevaluatedProperties: false6162properties:63data-lanes:64description: array of physical DSI data lane indexes.65minItems: 166items:67- const: 168- const: 269- const: 370- const: 47172port@1:73$ref: /schemas/graph.yaml#/properties/port74description:75Video port for MIPI DPI output (panel or connector).7677required:78- port@17980required:81- compatible82- reg83- enable-gpios84- ports8586additionalProperties: false8788examples:89- |90#include <dt-bindings/gpio/gpio.h>9192dsi {93#address-cells = <1>;94#size-cells = <0>;9596bridge@0 {97compatible = "chipone,icn6211";98reg = <0>;99enable-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* LCD-RST: PL5 */100101ports {102#address-cells = <1>;103#size-cells = <0>;104105port@0 {106reg = <0>;107108bridge_in_dsi: endpoint {109remote-endpoint = <&dsi_out_bridge>;110};111};112113port@1 {114reg = <1>;115116bridge_out_panel: endpoint {117remote-endpoint = <&panel_out_bridge>;118};119};120};121};122};123124125