fsl,imx8mp-hdmi-tx.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/fsl,imx8mp-hdmi-tx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale i.MX8MP DWC HDMI TX Encoder

maintainers:
  - Lucas Stach <[e-mail]>

description:
  The i.MX8MP HDMI transmitter is a Synopsys DesignWare
  HDMI 2.0a TX controller IP.

allOf:
  - $ref: /schemas/display/bridge/synopsys,dw-hdmi.yaml#

properties:
  compatible:
    enum:
      - fsl,imx8mp-hdmi-tx

  reg-io-width:
    const: 1

  clocks:
    maxItems: 4

  clock-names:
    items:
      - const: iahb
      - const: isfr
      - const: cec
      - const: pix

  power-domains:
    maxItems: 1

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/properties/port
        description: Parallel RGB input port

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description: HDMI output port

      port@2:
        $ref: /schemas/graph.yaml#/properties/port
        description: Parallel audio input port

    required:
      - port@0
      - port@1

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - interrupts
  - power-domains
  - ports

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx8mp-clock.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/power/imx8mp-power.h>

    hdmi@32fd8000 {
        compatible = "fsl,imx8mp-hdmi-tx";
        reg = <0x32fd8000 0x7eff>;
        interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&clk IMX8MP_CLK_HDMI_APB>,
                 <&clk IMX8MP_CLK_HDMI_REF_266M>,
                 <&clk IMX8MP_CLK_32K>,
                 <&hdmi_tx_phy>;
        clock-names = "iahb", "isfr", "cec", "pix";
        power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX>;
        reg-io-width = <1>;
        ports {
            #address-cells = <1>;
            #size-cells = <0>;
            port@0 {
                reg = <0>;

                endpoint {
                    remote-endpoint = <&pvi_to_hdmi_tx>;
                };
            };

            port@1 {
                reg = <1>;
                endpoint {
                    remote-endpoint = <&hdmi0_con>;
                };
            };

            port@2 {
                reg = <2>;

                endpoint {
                    remote-endpoint = <&pai_to_hdmi_tx>;
                };
            };
        };
    };