CoCalc -- renesas,dsi.yaml

GitHub Repository: torvalds/linux
Path: blob/master/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/bridge/renesas,dsi.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas RZ/G2L MIPI DSI Encoder
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maintainers:
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  - Biju Das <biju.das.jz@bp.renesas.com>
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description: |
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  This binding describes the MIPI DSI encoder embedded in the Renesas
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  RZ/G2L alike family of SoC's. The encoder can operate in DSI mode, with
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  up to four data lanes.
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allOf:
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  - $ref: /schemas/display/dsi-controller.yaml#
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properties:
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  compatible:
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    items:
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      - enum:
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          - renesas,r9a07g044-mipi-dsi # RZ/G2{L,LC}
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          - renesas,r9a07g054-mipi-dsi # RZ/V2L
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      - const: renesas,rzg2l-mipi-dsi
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  reg:
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    maxItems: 1
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  interrupts:
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    items:
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      - description: Sequence operation channel 0 interrupt
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      - description: Sequence operation channel 1 interrupt
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      - description: Video-Input operation channel 1 interrupt
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      - description: DSI Packet Receive interrupt
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      - description: DSI Fatal Error interrupt
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      - description: DSI D-PHY PPI interrupt
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      - description: Debug interrupt
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  interrupt-names:
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    items:
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      - const: seq0
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      - const: seq1
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      - const: vin1
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      - const: rcv
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      - const: ferr
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      - const: ppi
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      - const: debug
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  clocks:
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    items:
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      - description: DSI D-PHY PLL multiplied clock
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      - description: DSI D-PHY system clock
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      - description: DSI AXI bus clock
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      - description: DSI Register access clock
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      - description: DSI Video clock
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      - description: DSI D-PHY Escape mode transmit clock
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  clock-names:
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    items:
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      - const: pllclk
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      - const: sysclk
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      - const: aclk
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      - const: pclk
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      - const: vclk
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      - const: lpclk
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  resets:
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    items:
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      - description: MIPI_DSI_CMN_RSTB
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      - description: MIPI_DSI_ARESET_N
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      - description: MIPI_DSI_PRESET_N
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  reset-names:
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    items:
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      - const: rst
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      - const: arst
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      - const: prst
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  power-domains:
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    maxItems: 1
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  ports:
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    $ref: /schemas/graph.yaml#/properties/ports
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    properties:
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      port@0:
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        $ref: /schemas/graph.yaml#/properties/port
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        description: Parallel input port
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      port@1:
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        $ref: /schemas/graph.yaml#/$defs/port-base
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        unevaluatedProperties: false
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        description: DSI output port
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        properties:
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          endpoint:
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            $ref: /schemas/media/video-interfaces.yaml#
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            unevaluatedProperties: false
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            properties:
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              data-lanes:
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                description: array of physical DSI data lane indexes.
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                minItems: 1
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                items:
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                  - const: 1
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                  - const: 2
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                  - const: 3
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                  - const: 4
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            required:
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              - data-lanes
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    required:
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      - port@0
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      - port@1
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required:
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  - compatible
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  - reg
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  - interrupts
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  - interrupt-names
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  - clocks
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  - clock-names
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  - resets
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  - reset-names
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  - power-domains
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  - ports
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unevaluatedProperties: false
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examples:
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  - |
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    #include <dt-bindings/clock/r9a07g044-cpg.h>
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    #include <dt-bindings/interrupt-controller/arm-gic.h>
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    dsi0: dsi@10850000 {
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        compatible = "renesas,r9a07g044-mipi-dsi", "renesas,rzg2l-mipi-dsi";
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        reg = <0x10850000 0x20000>;
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        interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
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                     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
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                     <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
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                     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
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                     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
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                     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
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                     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
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        interrupt-names = "seq0", "seq1", "vin1", "rcv",
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                          "ferr", "ppi", "debug";
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        clocks = <&cpg CPG_MOD R9A07G044_MIPI_DSI_PLLCLK>,
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                 <&cpg CPG_MOD R9A07G044_MIPI_DSI_SYSCLK>,
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                 <&cpg CPG_MOD R9A07G044_MIPI_DSI_ACLK>,
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                 <&cpg CPG_MOD R9A07G044_MIPI_DSI_PCLK>,
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                 <&cpg CPG_MOD R9A07G044_MIPI_DSI_VCLK>,
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                 <&cpg CPG_MOD R9A07G044_MIPI_DSI_LPCLK>;
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        clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk";
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        resets = <&cpg R9A07G044_MIPI_DSI_CMN_RSTB>,
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                 <&cpg R9A07G044_MIPI_DSI_ARESET_N>,
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                 <&cpg R9A07G044_MIPI_DSI_PRESET_N>;
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        reset-names = "rst", "arst", "prst";
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        power-domains = <&cpg>;
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        ports {
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            #address-cells = <1>;
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            #size-cells = <0>;
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            port@0 {
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                reg = <0>;
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                dsi0_in: endpoint {
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                    remote-endpoint = <&du_out_dsi0>;
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                };
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            };
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            port@1 {
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                reg = <1>;
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                dsi0_out: endpoint {
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                    data-lanes = <1 2 3 4>;
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                    remote-endpoint = <&adv7535_in>;
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                };
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            };
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        };
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    };
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  - |
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    #include <dt-bindings/gpio/gpio.h>
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    dsi1: dsi@10860000 {
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        #address-cells = <1>;
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        #size-cells = <0>;
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        compatible = "renesas,r9a07g044-mipi-dsi", "renesas,rzg2l-mipi-dsi";
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        reg = <0x10860000 0x20000>;
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        interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
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                     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
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                     <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
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                     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
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                     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
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                     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
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                     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
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        interrupt-names = "seq0", "seq1", "vin1", "rcv",
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                          "ferr", "ppi", "debug";
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        clocks = <&cpg CPG_MOD R9A07G044_MIPI_DSI_PLLCLK>,
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                 <&cpg CPG_MOD R9A07G044_MIPI_DSI_SYSCLK>,
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                 <&cpg CPG_MOD R9A07G044_MIPI_DSI_ACLK>,
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                 <&cpg CPG_MOD R9A07G044_MIPI_DSI_PCLK>,
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                 <&cpg CPG_MOD R9A07G044_MIPI_DSI_VCLK>,
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                 <&cpg CPG_MOD R9A07G044_MIPI_DSI_LPCLK>;
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        clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk";
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        resets = <&cpg R9A07G044_MIPI_DSI_CMN_RSTB>,
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                 <&cpg R9A07G044_MIPI_DSI_ARESET_N>,
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                 <&cpg R9A07G044_MIPI_DSI_PRESET_N>;
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        reset-names = "rst", "arst", "prst";
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        power-domains = <&cpg>;
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        panel@0 {
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            compatible = "rocktech,jh057n00900";
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            reg = <0>;
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            vcc-supply = <&reg_2v8_p>;
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            iovcc-supply = <&reg_1v8_p>;
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            reset-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>;
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            port {
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                panel_in: endpoint {
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                    remote-endpoint = <&dsi1_out>;
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                };
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            };
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        };
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        ports {
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            #address-cells = <1>;
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            #size-cells = <0>;
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            port@0 {
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                reg = <0>;
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                dsi1_in: endpoint {
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                    remote-endpoint = <&du_out_dsi1>;
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                };
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            };
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            port@1 {
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                reg = <1>;
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                dsi1_out: endpoint {
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                    data-lanes = <1 2 3 4>;
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                    remote-endpoint = <&panel_in>;
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                };
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            };
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        };
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    };
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...
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