Path: blob/master/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)1%YAML 1.22---3$id: http://devicetree.org/schemas/display/bridge/samsung,mipi-dsim.yaml#4$schema: http://devicetree.org/meta-schemas/core.yaml#56title: Samsung MIPI DSIM bridge controller78maintainers:9- Inki Dae <inki.dae@samsung.com>10- Jagan Teki <jagan@amarulasolutions.com>11- Marek Szyprowski <m.szyprowski@samsung.com>1213description: |14Samsung MIPI DSIM bridge controller can be found it on Exynos15and i.MX8M Mini/Nano/Plus SoC's.1617properties:18compatible:19oneOf:20- enum:21- samsung,exynos3250-mipi-dsi22- samsung,exynos4210-mipi-dsi23- samsung,exynos5410-mipi-dsi24- samsung,exynos5422-mipi-dsi25- samsung,exynos5433-mipi-dsi26- fsl,imx8mm-mipi-dsim27- fsl,imx8mp-mipi-dsim28- items:29- enum:30- fsl,imx7d-mipi-dsim31- fsl,imx8mn-mipi-dsim32- const: fsl,imx8mm-mipi-dsim3334reg:35maxItems: 13637interrupts:38maxItems: 13940'#address-cells':41const: 14243'#size-cells':44const: 04546clocks:47minItems: 248maxItems: 54950clock-names:51minItems: 252maxItems: 55354samsung,phy-type:55$ref: /schemas/types.yaml#/definitions/uint3256description: phandle to the samsung phy-type5758power-domains:59maxItems: 16061samsung,power-domain:62$ref: /schemas/types.yaml#/definitions/phandle63description: phandle to the associated samsung power domain6465vddcore-supply:66description: MIPI DSIM Core voltage supply (e.g. 1.1V)6768vddio-supply:69description: MIPI DSIM I/O and PLL voltage supply (e.g. 1.8V)7071samsung,burst-clock-frequency:72$ref: /schemas/types.yaml#/definitions/uint3273description:74DSIM high speed burst mode frequency. If absent,75the pixel clock from the attached device or bridge76will be used instead.7778samsung,esc-clock-frequency:79$ref: /schemas/types.yaml#/definitions/uint3280description:81DSIM escape mode frequency.8283samsung,pll-clock-frequency:84$ref: /schemas/types.yaml#/definitions/uint3285description:86DSIM oscillator clock frequency. If absent, the clock frequency87of sclk_mipi will be used instead.8889phys:90maxItems: 19192phy-names:93const: dsim9495ports:96$ref: /schemas/graph.yaml#/properties/ports9798properties:99port@0:100$ref: /schemas/graph.yaml#/properties/port101description:102Input port node to receive pixel data from the103display controller. Exactly one endpoint must be104specified.105106port@1:107$ref: /schemas/graph.yaml#/$defs/port-base108unevaluatedProperties: false109description:110DSI output port node to the panel or the next bridge111in the chain.112113properties:114endpoint:115$ref: /schemas/media/video-interfaces.yaml#116unevaluatedProperties: false117118properties:119data-lanes:120minItems: 1121maxItems: 4122uniqueItems: true123items:124enum: [ 1, 2, 3, 4 ]125126lane-polarities:127minItems: 1128maxItems: 5129description:130The Samsung MIPI DSI IP requires that all the data lanes have131the same polarity.132133dependencies:134lane-polarities: [data-lanes]135136required:137- clock-names138- clocks139- compatible140- interrupts141- reg142- samsung,esc-clock-frequency143144allOf:145- $ref: ../dsi-controller.yaml#146- if:147properties:148compatible:149contains:150const: samsung,exynos5433-mipi-dsi151152then:153properties:154clocks:155minItems: 5156157clock-names:158items:159- const: bus_clk160- const: phyclk_mipidphy0_bitclkdiv8161- const: phyclk_mipidphy0_rxclkesc0162- const: sclk_rgb_vclk_to_dsim0163- const: sclk_mipi164165ports:166required:167- port@0168169required:170- ports171- vddcore-supply172- vddio-supply173174- if:175properties:176compatible:177contains:178const: samsung,exynos5410-mipi-dsi179180then:181properties:182clocks:183minItems: 2184185clock-names:186items:187- const: bus_clk188- const: pll_clk189190required:191- vddcore-supply192- vddio-supply193194- if:195properties:196compatible:197contains:198const: samsung,exynos4210-mipi-dsi199200then:201properties:202clocks:203minItems: 2204205clock-names:206items:207- const: bus_clk208- const: sclk_mipi209210required:211- vddcore-supply212- vddio-supply213214- if:215properties:216compatible:217contains:218const: samsung,exynos3250-mipi-dsi219220then:221properties:222clocks:223minItems: 2224225clock-names:226items:227- const: bus_clk228- const: pll_clk229230required:231- vddcore-supply232- vddio-supply233- samsung,phy-type234235additionalProperties:236type: object237238examples:239- |240#include <dt-bindings/clock/exynos5433.h>241#include <dt-bindings/gpio/gpio.h>242#include <dt-bindings/interrupt-controller/arm-gic.h>243244dsi@13900000 {245compatible = "samsung,exynos5433-mipi-dsi";246reg = <0x13900000 0xC0>;247interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;248phys = <&mipi_phy 1>;249phy-names = "dsim";250clocks = <&cmu_disp CLK_PCLK_DSIM0>,251<&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8>,252<&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0>,253<&cmu_disp CLK_SCLK_RGB_VCLK_TO_DSIM0>,254<&cmu_disp CLK_SCLK_DSIM0>;255clock-names = "bus_clk",256"phyclk_mipidphy0_bitclkdiv8",257"phyclk_mipidphy0_rxclkesc0",258"sclk_rgb_vclk_to_dsim0",259"sclk_mipi";260power-domains = <&pd_disp>;261vddcore-supply = <&ldo6_reg>;262vddio-supply = <&ldo7_reg>;263samsung,burst-clock-frequency = <512000000>;264samsung,esc-clock-frequency = <16000000>;265samsung,pll-clock-frequency = <24000000>;266pinctrl-names = "default";267pinctrl-0 = <&te_irq>;268269ports {270#address-cells = <1>;271#size-cells = <0>;272273port@0 {274reg = <0>;275276dsi_to_mic: endpoint {277remote-endpoint = <&mic_to_dsi>;278};279};280};281};282283284