Path: blob/master/Documentation/devicetree/bindings/display/bridge/sil,sii8620.yaml
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause1%YAML 1.22---3$id: http://devicetree.org/schemas/display/bridge/sil,sii8620.yaml#4$schema: http://devicetree.org/meta-schemas/core.yaml#56title: Silicon Image SiI8620 HDMI/MHL bridge78maintainers:9- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>1011properties:12compatible:13const: sil,sii86201415reg:16maxItems: 11718clocks:19maxItems: 12021clock-names:22items:23- const: xtal2425cvcc10-supply:26description: Digital Core Supply Voltage (1.0V)2728interrupts:29maxItems: 13031iovcc18-supply:32description: I/O Supply Voltage (1.8V)3334reset-gpios:35maxItems: 13637ports:38$ref: /schemas/graph.yaml#/properties/ports39unevaluatedProperties: false4041properties:42port@0:43$ref: /schemas/graph.yaml#/properties/port44description:45Video port for HDMI (encoder) input4647port@1:48$ref: /schemas/graph.yaml#/properties/port49description:50MHL to connector port5152required:53- port@054- port@15556required:57- compatible58- reg59- clocks60- cvcc10-supply61- interrupts62- iovcc18-supply63- reset-gpios64- ports6566additionalProperties: false6768examples:69- |70#include <dt-bindings/gpio/gpio.h>71#include <dt-bindings/interrupt-controller/irq.h>7273i2c {74#address-cells = <1>;75#size-cells = <0>;7677bridge@39 {78reg = <0x39>;79compatible = "sil,sii8620";80cvcc10-supply = <&ldo36_reg>;81iovcc18-supply = <&ldo34_reg>;82interrupt-parent = <&gpf0>;83interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;84reset-gpios = <&gpv7 0 GPIO_ACTIVE_LOW>;85clocks = <&pmu_system_controller 0>;86clock-names = "xtal";8788ports {89#address-cells = <1>;90#size-cells = <0>;9192port@0 {93reg = <0>;94mhl_to_hdmi: endpoint {95remote-endpoint = <&hdmi_to_mhl>;96};97};9899port@1 {100reg = <1>;101mhl_to_musb_con: endpoint {102remote-endpoint = <&musb_con_to_mhl>;103};104};105};106};107};108109110