Path: blob/master/Documentation/devicetree/bindings/display/bridge/sil,sii9022.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)1%YAML 1.22---3$id: http://devicetree.org/schemas/display/bridge/sil,sii9022.yaml#4$schema: http://devicetree.org/meta-schemas/core.yaml#56title: Silicon Image sii902x HDMI bridge78maintainers:9- Boris Brezillon <bbrezillon@kernel.org>1011properties:12compatible:13oneOf:14- items:15- enum:16- sil,sii9022-cpi # CEC Programming Interface17- sil,sii9022-tpi # Transmitter Programming Interface18- const: sil,sii902219- const: sil,sii90222021reg:22maxItems: 12324interrupts:25maxItems: 126description: Interrupt line used to inform the host about hotplug events.2728reset-gpios:29maxItems: 13031iovcc-supply:32description: I/O Supply Voltage (1.8V or 3.3V)3334cvcc12-supply:35description: Digital Core Supply Voltage (1.2V)3637'#sound-dai-cells':38enum: [ 0, 1 ]39description: |40<0> if only I2S or S/PDIF pin is wired,41<1> if both are wired.42HDMI audio is configured only if this property is found.43If HDMI audio is configured, the sii902x device becomes an I2S and/or44S/PDIF audio codec component (e.g. a digital audio sink), that can be45used in configuring full audio devices with simple-card or46audio-graph-card bindings. See their binding documents on how to describe47the way the48sii902x device is connected to the rest of the audio system:49Documentation/devicetree/bindings/sound/simple-card.yaml50Documentation/devicetree/bindings/sound/audio-graph-card.yaml51Note: In case of the audio-graph-card binding the used port index should52be 3.5354sil,i2s-data-lanes:55$ref: /schemas/types.yaml#/definitions/uint32-array56minItems: 157maxItems: 458uniqueItems: true59items:60enum: [ 0, 1, 2, 3 ]61description:62Each integer indicates which I2S pin is connected to which audio FIFO.63The first integer selects the I2S audio pin for the first audio FIFO#064(HDMI channels 1&2), the second for FIFO#1 (HDMI channels 3&4), and so65on. There are 4 FIFOs and 4 I2S pins (SD0 - SD3). Any I2S pin can be66connected to any FIFO, but there can be no gaps. E.g. an I2S pin must be67mapped to FIFO#0 and FIFO#1 before mapping a channel to FIFO#2. The68default value is <0>, describing SD0 pin being routed to HDMI audio69FIFO#0.7071clocks:72maxItems: 173description: MCLK input. MCLK can be used to produce HDMI audio CTS values.7475clock-names:76const: mclk7778ports:79$ref: /schemas/graph.yaml#/properties/ports8081properties:82port@0:83unevaluatedProperties: false84$ref: /schemas/graph.yaml#/$defs/port-base85description: Parallel RGB input port8687properties:88endpoint:89$ref: /schemas/graph.yaml#/$defs/endpoint-base90unevaluatedProperties: false9192properties:93bus-width:94description:95Endpoint bus width.96enum: [ 16, 18, 24 ]97default: 249899port@1:100$ref: /schemas/graph.yaml#/properties/port101description: HDMI output port102103port@3:104$ref: /schemas/graph.yaml#/properties/port105description: Sound input port106107required:108- compatible109- reg110111additionalProperties: false112113examples:114- |115i2c {116#address-cells = <1>;117#size-cells = <0>;118119hdmi-bridge@39 {120compatible = "sil,sii9022";121reg = <0x39>;122reset-gpios = <&pioA 1 0>;123iovcc-supply = <&v3v3_hdmi>;124cvcc12-supply = <&v1v2_hdmi>;125126#sound-dai-cells = <0>;127sil,i2s-data-lanes = < 0 1 2 >;128clocks = <&mclk>;129clock-names = "mclk";130131ports {132#address-cells = <1>;133#size-cells = <0>;134135port@0 {136reg = <0>;137bridge_in: endpoint {138remote-endpoint = <&dc_out>;139};140};141};142};143};144145146