Path: blob/master/Documentation/devicetree/bindings/display/bridge/thead,th1520-dw-hdmi.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)1%YAML 1.22---3$id: http://devicetree.org/schemas/display/bridge/thead,th1520-dw-hdmi.yaml#4$schema: http://devicetree.org/meta-schemas/core.yaml#56title: T-Head TH1520 DesignWare HDMI TX Encoder78maintainers:9- Icenowy Zheng <uwu@icenowy.me>1011description:12The HDMI transmitter is a Synopsys DesignWare HDMI TX controller13paired with a DesignWare HDMI Gen2 TX PHY.1415allOf:16- $ref: /schemas/display/bridge/synopsys,dw-hdmi.yaml#1718properties:19compatible:20enum:21- thead,th1520-dw-hdmi2223reg-io-width:24const: 42526clocks:27maxItems: 42829clock-names:30items:31- const: iahb32- const: isfr33- const: cec34- const: pix3536resets:37items:38- description: Main reset39- description: Configuration APB reset4041reset-names:42items:43- const: main44- const: apb4546ports:47$ref: /schemas/graph.yaml#/properties/ports4849properties:50port@0:51$ref: /schemas/graph.yaml#/properties/port52description: Input port connected to DC8200 DPU "DP" output5354port@1:55$ref: /schemas/graph.yaml#/properties/port56description: HDMI output port5758required:59- port@060- port@16162required:63- compatible64- reg65- reg-io-width66- clocks67- clock-names68- resets69- reset-names70- interrupts71- ports7273unevaluatedProperties: false7475examples:76- |77#include <dt-bindings/interrupt-controller/irq.h>78#include <dt-bindings/clock/thead,th1520-clk-ap.h>79#include <dt-bindings/reset/thead,th1520-reset.h>8081soc {82#address-cells = <2>;83#size-cells = <2>;8485hdmi@ffef540000 {86compatible = "thead,th1520-dw-hdmi";87reg = <0xff 0xef540000 0x0 0x40000>;88reg-io-width = <4>;89interrupts = <111 IRQ_TYPE_LEVEL_HIGH>;90clocks = <&clk_vo CLK_HDMI_PCLK>,91<&clk_vo CLK_HDMI_SFR>,92<&clk_vo CLK_HDMI_CEC>,93<&clk_vo CLK_HDMI_PIXCLK>;94clock-names = "iahb", "isfr", "cec", "pix";95resets = <&rst_vo TH1520_RESET_ID_HDMI>,96<&rst_vo TH1520_RESET_ID_HDMI_APB>;97reset-names = "main", "apb";9899ports {100#address-cells = <1>;101#size-cells = <0>;102port@0 {103reg = <0>;104105hdmi_in: endpoint {106remote-endpoint = <&dpu_out_dp1>;107};108};109110port@1 {111reg = <1>;112113hdmi_out_conn: endpoint {114remote-endpoint = <&hdmi_conn_in>;115};116};117};118};119};120121122