Path: blob/master/Documentation/devicetree/bindings/display/bridge/thine,thc63lvd1024.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)1%YAML 1.22---3$id: http://devicetree.org/schemas/display/bridge/thine,thc63lvd1024.yaml#4$schema: http://devicetree.org/meta-schemas/core.yaml#56title: Thine Electronics THC63LVD1024 LVDS Decoder78maintainers:9- Jacopo Mondi <jacopo+renesas@jmondi.org>10- Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>1112description: |13The THC63LVD1024 is a dual link LVDS receiver designed to convert LVDS14streams to parallel data outputs. The chip supports single/dual input/output15modes, handling up to two LVDS input streams and up to two digital CMOS/TTL16outputs.1718Single or dual operation mode, output data mapping and DDR output modes are19configured through input signals and the chip does not expose any control20bus.2122properties:23compatible:24const: thine,thc63lvd10242526ports:27$ref: /schemas/graph.yaml#/properties/ports28description: |29The device can operate in single or dual input and output modes.3031When operating in single input mode, all pixels are received on port@0,32and port@1 shall not contain any endpoint. In dual input mode,33even-numbered pixels are received on port@0 and odd-numbered pixels on34port@1, and both port@0 and port@1 shall contain endpoints.3536When operating in single output mode all pixels are output from the first37CMOS/TTL port and port@3 shall not contain any endpoint. In dual output38mode pixels are output from both CMOS/TTL ports and both port@2 and39port@3 shall contain endpoints.4041properties:42port@0:43$ref: /schemas/graph.yaml#/properties/port44description: First LVDS input port4546port@1:47$ref: /schemas/graph.yaml#/properties/port48description: Second LVDS input port4950port@2:51$ref: /schemas/graph.yaml#/properties/port52description: First digital CMOS/TTL parallel output5354port@3:55$ref: /schemas/graph.yaml#/properties/port56description: Second digital CMOS/TTL parallel output5758required:59- port@060- port@26162oe-gpios:63maxItems: 164description: Output enable GPIO signal, pin name "OE", active high.6566powerdown-gpios:67maxItems: 168description: Power down GPIO signal, pin name "/PDWN", active low.6970vcc-supply:71description:72Power supply for the TTL output, TTL CLOCKOUT signal, LVDS input, PLL and73digital circuitry.7475required:76- compatible77- ports78- vcc-supply7980additionalProperties: false8182examples:83- |84#include <dt-bindings/gpio/gpio.h>8586lvds-decoder {87compatible = "thine,thc63lvd1024";8889vcc-supply = <®_lvds_vcc>;90powerdown-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;9192ports {93#address-cells = <1>;94#size-cells = <0>;9596port@0 {97reg = <0>;9899lvds_dec_in_0: endpoint {100remote-endpoint = <&lvds_out>;101};102};103104port@2 {105reg = <2>;106107lvds_dec_out_2: endpoint {108remote-endpoint = <&adv7511_in>;109};110};111};112};113114...115116117