Path: blob/master/Documentation/devicetree/bindings/dma/altr,msgdma.yaml
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause1%YAML 1.22---3$id: http://devicetree.org/schemas/dma/altr,msgdma.yaml#4$schema: http://devicetree.org/meta-schemas/core.yaml#56title: Altera mSGDMA IP core78maintainers:9- Olivier Dautricourt <olivierdautricourt@gmail.com>1011description: |12Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA)13intellectual property (IP)1415allOf:16- $ref: dma-controller.yaml#1718properties:19compatible:20const: altr,socfpga-msgdma2122reg:23items:24- description: Control and Status Register Slave Port25- description: Descriptor Slave Port26- description: Response Slave Port (Optional)27minItems: 22829reg-names:30items:31- const: csr32- const: desc33- const: resp34minItems: 23536interrupts:37maxItems: 13839"#dma-cells":40const: 141description:42The cell identifies the channel id (must be 0)4344required:45- compatible46- reg47- reg-names48- interrupts4950unevaluatedProperties: false5152examples:53- |54#include <dt-bindings/interrupt-controller/irq.h>5556msgdma_controller: dma-controller@ff200b00 {57compatible = "altr,socfpga-msgdma";58reg = <0xff200b00 0x100>, <0xff200c00 0x100>, <0xff200d00 0x100>;59reg-names = "csr", "desc", "resp";60interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;61#dma-cells = <1>;62};636465