Path: blob/master/Documentation/devicetree/bindings/dma/apm,xgene-storm-dma.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)1%YAML 1.22---3$id: http://devicetree.org/schemas/dma/apm,xgene-storm-dma.yaml#4$schema: http://devicetree.org/meta-schemas/core.yaml#56title: APM X-Gene Storm SoC DMA78maintainers:9- Khuong Dinh <khuong@os.amperecomputing.com>1011properties:12compatible:13const: apm,xgene-storm-dma1415reg:16items:17- description: DMA control and status registers18- description: Descriptor ring control and status registers19- description: Descriptor ring command registers20- description: SoC efuse registers2122interrupts:23items:24- description: DMA error reporting interrupt25- description: DMA channel 0 completion interrupt26- description: DMA channel 1 completion interrupt27- description: DMA channel 2 completion interrupt28- description: DMA channel 3 completion interrupt2930clocks:31maxItems: 13233dma-coherent: true3435required:36- compatible37- reg38- interrupts39- clocks4041additionalProperties: false4243examples:44- |45dma@1f270000 {46compatible = "apm,xgene-storm-dma";47reg = <0x1f270000 0x10000>,48<0x1f200000 0x10000>,49<0x1b000000 0x400000>,50<0x1054a000 0x100>;51interrupts = <0x0 0x82 0x4>,52<0x0 0xb8 0x4>,53<0x0 0xb9 0x4>,54<0x0 0xba 0x4>,55<0x0 0xbb 0x4>;56dma-coherent;57clocks = <&dmaclk 0>;58};596061