Path: blob/master/Documentation/devicetree/bindings/dma/arm-pl08x.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)1%YAML 1.22---3$id: http://devicetree.org/schemas/dma/arm-pl08x.yaml#4$schema: http://devicetree.org/meta-schemas/core.yaml#56title: ARM PrimeCells PL080 and PL081 and derivatives DMA controller78maintainers:9- Vinod Koul <vkoul@kernel.org>1011allOf:12- $ref: /schemas/arm/primecell.yaml#13- $ref: dma-controller.yaml#1415# We need a select here so we don't match all nodes with 'arm,primecell'16select:17properties:18compatible:19contains:20enum:21- arm,pl08022- arm,pl08123required:24- compatible2526properties:27compatible:28oneOf:29- items:30- enum:31- arm,pl08032- arm,pl08133- const: arm,primecell34- items:35- const: faraday,ftdma02036- const: arm,pl08037- const: arm,primecell3839reg:40maxItems: 141description: Address range of the PL08x registers4243interrupts:44minItems: 145description: The PL08x interrupt number4647clocks:48minItems: 149description: The clock running the IP core clock5051clock-names:52maxItems: 15354lli-bus-interface-ahb1:55type: boolean56description: if AHB master 1 is eligible for fetching LLIs5758lli-bus-interface-ahb2:59type: boolean60description: if AHB master 2 is eligible for fetching LLIs6162mem-bus-interface-ahb1:63type: boolean64description: if AHB master 1 is eligible for fetching memory contents6566mem-bus-interface-ahb2:67type: boolean68description: if AHB master 2 is eligible for fetching memory contents6970memcpy-burst-size:71$ref: /schemas/types.yaml#/definitions/uint3272enum:73- 174- 475- 876- 1677- 3278- 6479- 12880- 25681description: the size of the bursts for memcpy8283memcpy-bus-width:84$ref: /schemas/types.yaml#/definitions/uint3285enum:86- 887- 1688- 3289- 6490description: bus width used for memcpy in bits. FTDMAC020 also accept 64 bits9192resets:93maxItems: 19495required:96- reg97- interrupts98- clocks99- clock-names100- "#dma-cells"101102unevaluatedProperties: false103104examples:105- |106dmac0: dma-controller@10130000 {107compatible = "arm,pl080", "arm,primecell";108reg = <0x10130000 0x1000>;109interrupt-parent = <&vica>;110interrupts = <15>;111clocks = <&hclkdma0>;112clock-names = "apb_pclk";113lli-bus-interface-ahb1;114lli-bus-interface-ahb2;115mem-bus-interface-ahb2;116memcpy-burst-size = <256>;117memcpy-bus-width = <32>;118#dma-cells = <2>;119};120- |121#include <dt-bindings/interrupt-controller/irq.h>122#include <dt-bindings/reset/cortina,gemini-reset.h>123#include <dt-bindings/clock/cortina,gemini-clock.h>124dma-controller@67000000 {125compatible = "faraday,ftdma020", "arm,pl080", "arm,primecell";126/* Faraday Technology FTDMAC020 variant */127arm,primecell-periphid = <0x0003b080>;128reg = <0x67000000 0x1000>;129interrupts = <9 IRQ_TYPE_EDGE_RISING>;130resets = <&syscon GEMINI_RESET_DMAC>;131clocks = <&syscon GEMINI_CLK_AHB>;132clock-names = "apb_pclk";133/* Bus interface AHB1 (AHB0) is totally tilted */134lli-bus-interface-ahb2;135mem-bus-interface-ahb2;136memcpy-burst-size = <256>;137memcpy-bus-width = <32>;138#dma-cells = <2>;139};140141142