Path: blob/master/Documentation/devicetree/bindings/dma/atmel,sama5d4-dma.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)1%YAML 1.22---3$id: http://devicetree.org/schemas/dma/atmel,sama5d4-dma.yaml#4$schema: http://devicetree.org/meta-schemas/core.yaml#56title: Microchip AT91 Extensible Direct Memory Access Controller78maintainers:9- Nicolas Ferre <nicolas.ferre@microchip.com>10- Charan Pedumuru <charan.pedumuru@microchip.com>1112description:13The DMA Controller (XDMAC) is a AHB-protocol central direct memory access14controller. It performs peripheral data transfer and memory move operations15over one or two bus ports through the unidirectional communication16channel. Each channel is fully programmable and provides both peripheral17or memory-to-memory transfers. The channel features are configurable at18implementation.1920allOf:21- $ref: dma-controller.yaml#2223properties:24compatible:25oneOf:26- enum:27- atmel,sama5d4-dma28- microchip,sama7g5-dma29- items:30- enum:31- microchip,sam9x60-dma32- microchip,sam9x7-dma33- const: atmel,sama5d4-dma34- items:35- const: microchip,sama7d65-dma36- const: microchip,sama7g5-dma3738"#dma-cells":39description: |40Represents the number of integer cells in the `dmas` property of client41devices. The single cell specifies the channel configuration register:42- bit 13: SIF (Source Interface Identifier) for memory interface.43- bit 14: DIF (Destination Interface Identifier) for peripheral interface.44- bit 30-24: PERID (Peripheral Identifier).45const: 14647reg:48maxItems: 14950interrupts:51maxItems: 15253clocks:54maxItems: 15556clock-names:57const: dma_clk5859required:60- compatible61- reg62- interrupts63- clocks64- clock-names65- "#dma-cells"6667unevaluatedProperties: false6869examples:70- |71#include <dt-bindings/clock/at91.h>72#include <dt-bindings/dma/at91.h>73#include <dt-bindings/interrupt-controller/irq.h>74dma-controller@f0008000 {75compatible = "atmel,sama5d4-dma";76reg = <0xf0008000 0x1000>;77interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;78#dma-cells = <1>;79clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;80clock-names = "dma_clk";81};828384