Path: blob/master/Documentation/devicetree/bindings/dma/ingenic,dma.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)1%YAML 1.22---3$id: http://devicetree.org/schemas/dma/ingenic,dma.yaml#4$schema: http://devicetree.org/meta-schemas/core.yaml#56title: Ingenic SoCs DMA Controller78maintainers:9- Paul Cercueil <paul@crapouillou.net>1011allOf:12- $ref: dma-controller.yaml#1314properties:15compatible:16oneOf:17- enum:18- ingenic,jz4740-dma19- ingenic,jz4725b-dma20- ingenic,jz4755-dma21- ingenic,jz4760-dma22- ingenic,jz4760-bdma23- ingenic,jz4760-mdma24- ingenic,jz4760b-dma25- ingenic,jz4760b-bdma26- ingenic,jz4760b-mdma27- ingenic,jz4770-dma28- ingenic,jz4780-dma29- ingenic,x1000-dma30- ingenic,x1830-dma31- items:32- const: ingenic,jz4770-bdma33- const: ingenic,jz4760b-bdma3435reg:36items:37- description: Channel-specific registers38- description: System control registers3940interrupts:41maxItems: 14243clocks:44maxItems: 14546"#dma-cells":47enum: [2, 3]48description: >49DMA clients must use the format described in dma.txt, giving a phandle50to the DMA controller plus the following integer cells:5152- Request type: The DMA request type specifies the device endpoint that53will be the source or destination of the DMA transfer.54If "#dma-cells" is 2, the request type is a single cell, and the55direction will be unidirectional (either RX or TX but not both).56If "#dma-cells" is 3, the request type has two cells; the first57one corresponds to the host to device direction (TX), the second one58corresponds to the device to host direction (RX). The DMA channel is59then bidirectional.6061- Channel: If set to 0xffffffff, any available channel will be allocated62for the client. Otherwise, the exact channel specified will be used.63The channel should be reserved on the DMA controller using the64ingenic,reserved-channels property.6566ingenic,reserved-channels:67$ref: /schemas/types.yaml#/definitions/uint3268description: >69Bitmask of channels to reserve for devices that need a specific70channel. These channels will only be assigned when explicitly71requested by a client. The primary use for this is channels 0 and721, which can be configured to have special behaviour for NAND/BCH73when using programmable firmware.7475required:76- compatible77- reg78- interrupts79- clocks8081unevaluatedProperties: false8283examples:84- |85#include <dt-bindings/clock/ingenic,jz4780-cgu.h>86dma: dma-controller@13420000 {87compatible = "ingenic,jz4780-dma";88reg = <0x13420000 0x400>, <0x13421000 0x40>;8990interrupt-parent = <&intc>;91interrupts = <10>;9293clocks = <&cgu JZ4780_CLK_PDMA>;9495#dma-cells = <2>;9697ingenic,reserved-channels = <0x3>;98};99100101