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torvalds
GitHub Repository: torvalds/linux
 Path: blob/master/Documentation/devicetree/bindings/dma/nvidia,tegra20-apbdma.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

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%YAML 1.2

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---

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$id: http://devicetree.org/schemas/dma/nvidia,tegra20-apbdma.yaml#

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$schema: http://devicetree.org/meta-schemas/core.yaml#

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title: NVIDIA Tegra APB DMA Controller

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description:

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  The NVIDIA Tegra APB DMA controller is a hardware component that

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  enables direct memory access (DMA) on Tegra systems. It facilitates

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  data transfer between I/O devices and main memory without constant

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  CPU intervention.

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maintainers:

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  - Jonathan Hunter <jonathanh@nvidia.com>

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properties:

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  compatible:

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    oneOf:

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      - const: nvidia,tegra20-apbdma

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      - items:

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          - const: nvidia,tegra30-apbdma

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          - const: nvidia,tegra20-apbdma

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  reg:

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    maxItems: 1

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  "#dma-cells":

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    const: 1

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  clocks:

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    maxItems: 1

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  interrupts:

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    description:

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      Should contain all of the per-channel DMA interrupts in

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      ascending order with respect to the DMA channel index.

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    minItems: 1

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    maxItems: 32

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  resets:

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    maxItems: 1

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  reset-names:

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    const: dma

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required:

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  - compatible

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  - reg

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  - "#dma-cells"

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  - clocks

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  - interrupts

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  - resets

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  - reset-names

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allOf:

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  - $ref: dma-controller.yaml#

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unevaluatedProperties: false

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examples:

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  - |

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    #include <dt-bindings/interrupt-controller/arm-gic.h>

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    #include <dt-bindings/reset/tegra186-reset.h>

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    dma-controller@6000a000 {

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        compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";

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        reg = <0x6000a000 0x1200>;

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        interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,

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                     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,

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                     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,

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                     <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,

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                     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,

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                     <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,

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                     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,

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                     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,

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                     <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,

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                     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,

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                     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,

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                     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,

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                     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,

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                     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,

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                     <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,

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                     <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;

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        clocks = <&tegra_car 34>;

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        resets = <&tegra_car 34>;

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        reset-names = "dma";

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        #dma-cells = <1>;

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    };

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...

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