Path: blob/master/Documentation/devicetree/bindings/dma/owl-dma.yaml
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# SPDX-License-Identifier: GPL-2.01%YAML 1.22---3$id: http://devicetree.org/schemas/dma/owl-dma.yaml#4$schema: http://devicetree.org/meta-schemas/core.yaml#56title: Actions Semi Owl SoCs DMA controller78description: |9The OWL DMA is a general-purpose direct memory access controller capable of10supporting 10 independent DMA channels for the Actions Semi S700 SoC and 1211independent DMA channels for the S500 and S900 SoC variants.1213maintainers:14- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>1516allOf:17- $ref: dma-controller.yaml#1819properties:20compatible:21enum:22- actions,s500-dma23- actions,s700-dma24- actions,s900-dma2526reg:27maxItems: 12829interrupts:30description:31controller supports 4 interrupts, which are freely assignable to the32DMA channels.33maxItems: 43435"#dma-cells":36const: 13738dma-channels:39maximum: 124041dma-requests:42maximum: 464344clocks:45maxItems: 146description:47Phandle and Specifier of the clock feeding the DMA controller.4849power-domains:50maxItems: 15152required:53- compatible54- reg55- interrupts56- "#dma-cells"57- dma-channels58- dma-requests59- clocks6061unevaluatedProperties: false6263examples:64- |65#include <dt-bindings/interrupt-controller/arm-gic.h>66dma: dma-controller@e0260000 {67compatible = "actions,s900-dma";68reg = <0xe0260000 0x1000>;69interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,70<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,71<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,72<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;73#dma-cells = <1>;74dma-channels = <12>;75dma-requests = <46>;76clocks = <&clock 22>;77};7879...808182