Path: blob/master/Documentation/devicetree/bindings/dpll/dpll-device.yaml
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)1%YAML 1.22---3$id: http://devicetree.org/schemas/dpll/dpll-device.yaml#4$schema: http://devicetree.org/meta-schemas/core.yaml#56title: Digital Phase-Locked Loop (DPLL) Device78maintainers:9- Ivan Vecera <ivecera@redhat.com>1011description:12Digital Phase-Locked Loop (DPLL) device is used for precise clock13synchronization in networking and telecom hardware. The device can14have one or more channels (DPLLs) and one or more physical input and15output pins. Each DPLL channel can either produce pulse-per-clock signal16or drive ethernet equipment clock. The type of each channel can be17indicated by dpll-types property.1819properties:20$nodename:21pattern: "^dpll(@.*)?$"2223"#address-cells":24const: 02526"#size-cells":27const: 02829dpll-types:30description: List of DPLL channel types, one per DPLL instance.31$ref: /schemas/types.yaml#/definitions/non-unique-string-array32items:33enum: [pps, eec]3435input-pins:36type: object37description: DPLL input pins38unevaluatedProperties: false3940properties:41"#address-cells":42const: 143"#size-cells":44const: 04546patternProperties:47"^pin@[0-9a-f]+$":48$ref: /schemas/dpll/dpll-pin.yaml49unevaluatedProperties: false5051required:52- "#address-cells"53- "#size-cells"5455output-pins:56type: object57description: DPLL output pins58unevaluatedProperties: false5960properties:61"#address-cells":62const: 163"#size-cells":64const: 06566patternProperties:67"^pin@[0-9]+$":68$ref: /schemas/dpll/dpll-pin.yaml69unevaluatedProperties: false7071required:72- "#address-cells"73- "#size-cells"7475additionalProperties: true767778