Path: blob/master/Documentation/devicetree/bindings/dsp/fsl,dsp.yaml
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)1%YAML 1.22---3$id: http://devicetree.org/schemas/dsp/fsl,dsp.yaml#4$schema: http://devicetree.org/meta-schemas/core.yaml#56title: NXP i.MX8 DSP core78maintainers:9- Daniel Baluta <daniel.baluta@nxp.com>10- Shengjiu Wang <shengjiu.wang@nxp.com>1112description: |13Some boards from i.MX8 family contain a DSP core used for14advanced pre- and post- audio processing.1516properties:17compatible:18enum:19- fsl,imx8qxp-dsp20- fsl,imx8qm-dsp21- fsl,imx8mp-dsp22- fsl,imx8ulp-dsp23- fsl,imx8qxp-hifi424- fsl,imx8qm-hifi425- fsl,imx8mp-hifi426- fsl,imx8ulp-hifi42728reg:29maxItems: 13031clocks:32items:33- description: ipg clock34- description: ocram clock35- description: core clock36- description: debug interface clock37- description: message unit clock38minItems: 33940clock-names:41items:42- const: ipg43- const: ocram44- const: core45- const: debug46- const: mu47minItems: 34849power-domains:50description:51List of phandle and PM domain specifier as documented in52Documentation/devicetree/bindings/power/power_domain.txt53minItems: 154maxItems: 45556mboxes:57description:58List of <&phandle type channel> - 2 channels for TXDB, 2 channels for RXDB59or - 1 channel for TX, 1 channel for RX, 1 channel for RXDB60(see mailbox/fsl,mu.txt)61minItems: 362maxItems: 46364mbox-names:65minItems: 366maxItems: 46768memory-region:69description:70phandle to a node describing reserved memory (System RAM memory)71used by DSP (see bindings/reserved-memory/reserved-memory.txt)72minItems: 173maxItems: 47475firmware-name:76description: |77Default name of the firmware to load to the remote processor.7879fsl,dsp-ctrl:80$ref: /schemas/types.yaml#/definitions/phandle81description:82Phandle to syscon block which provide access for processor enablement8384resets:85minItems: 18687reset-names:88minItems: 189items:90- const: runstall91- const: softreset9293access-controllers:94maxItems: 19596required:97- compatible98- reg99- clocks100- clock-names101- power-domains102- mboxes103- mbox-names104- memory-region105106allOf:107- if:108properties:109compatible:110contains:111enum:112- fsl,imx8qxp-dsp113- fsl,imx8qxp-hifi4114then:115properties:116power-domains:117minItems: 2118maxItems: 2119120- if:121properties:122compatible:123contains:124enum:125- fsl,imx8qm-dsp126- fsl,imx8qm-hifi4127then:128properties:129power-domains:130minItems: 4131132- if:133properties:134compatible:135contains:136enum:137- fsl,imx8mp-dsp138- fsl,imx8mp-hifi4139- fsl,imx8ulp-dsp140- fsl,imx8ulp-hifi4141then:142properties:143power-domains:144maxItems: 1145146- if:147properties:148compatible:149contains:150enum:151- fsl,imx8qxp-hifi4152- fsl,imx8qm-hifi4153- fsl,imx8mp-hifi4154- fsl,imx8ulp-hifi4155then:156properties:157memory-region:158minItems: 4159mboxes:160maxItems: 3161mbox-names:162items:163- const: tx164- const: rx165- const: rxdb166else:167properties:168memory-region:169maxItems: 1170mboxes:171minItems: 4172mbox-names:173items:174- const: txdb0175- const: txdb1176- const: rxdb0177- const: rxdb1178- if:179properties:180compatible:181contains:182enum:183- fsl,imx8mp-dsp184- fsl,imx8mp-hifi4185then:186required:187- resets188- reset-names189190additionalProperties: false191192examples:193- |194#include <dt-bindings/firmware/imx/rsrc.h>195#include <dt-bindings/clock/imx8-clock.h>196dsp@596e8000 {197compatible = "fsl,imx8qxp-dsp";198reg = <0x596e8000 0x88000>;199clocks = <&adma_lpcg IMX_ADMA_LPCG_DSP_IPG_CLK>,200<&adma_lpcg IMX_ADMA_LPCG_OCRAM_IPG_CLK>,201<&adma_lpcg IMX_ADMA_LPCG_DSP_CORE_CLK>;202clock-names = "ipg", "ocram", "core";203power-domains = <&pd IMX_SC_R_MU_13B>,204<&pd IMX_SC_R_MU_2A>;205mbox-names = "txdb0", "txdb1", "rxdb0", "rxdb1";206mboxes = <&lsio_mu13 2 0>, <&lsio_mu13 2 1>, <&lsio_mu13 3 0>, <&lsio_mu13 3 1>;207memory-region = <&dsp_reserved>;208};209- |210#include <dt-bindings/clock/imx8mp-clock.h>211#include <dt-bindings/reset/imx8mp-reset-audiomix.h>212dsp_reserved: dsp@92400000 {213reg = <0x92400000 0x1000000>;214no-map;215};216dsp_vdev0vring0: vdev0vring0@942f0000 {217reg = <0x942f0000 0x8000>;218no-map;219};220dsp_vdev0vring1: vdev0vring1@942f8000 {221reg = <0x942f8000 0x8000>;222no-map;223};224dsp_vdev0buffer: vdev0buffer@94300000 {225compatible = "shared-dma-pool";226reg = <0x94300000 0x100000>;227no-map;228};229230dsp: dsp@3b6e8000 {231compatible = "fsl,imx8mp-hifi4";232reg = <0x3b6e8000 0x88000>;233clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_DSP_ROOT>,234<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_OCRAMA_IPG>,235<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_DSP_ROOT>,236<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_DSPDBG_ROOT>;237clock-names = "ipg", "ocram", "core", "debug";238firmware-name = "imx/dsp/hifi4.bin";239power-domains = <&audiomix_pd>;240mbox-names = "tx", "rx", "rxdb";241mboxes = <&mu2 0 0>,242<&mu2 1 0>,243<&mu2 3 0>;244memory-region = <&dsp_vdev0buffer>, <&dsp_vdev0vring0>,245<&dsp_vdev0vring1>, <&dsp_reserved>;246resets = <&audio_blk_ctrl IMX8MP_AUDIOMIX_DSP_RUNSTALL>;247reset-names = "runstall";248};249250251