Path: blob/master/Documentation/devicetree/bindings/dsp/mediatek,mt8195-dsp.yaml
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)1%YAML 1.22---3$id: http://devicetree.org/schemas/dsp/mediatek,mt8195-dsp.yaml#4$schema: http://devicetree.org/meta-schemas/core.yaml#56title: Mediatek mt8195 DSP core78maintainers:9- YC Hung <yc.hung@mediatek.com>1011description: |12Some boards from mt8195 contain a DSP core used for13advanced pre- and post- audio processing.1415properties:16compatible:17const: mediatek,mt8195-dsp1819reg:20items:21- description: Address and size of the DSP Cfg registers22- description: Address and size of the DSP SRAM2324reg-names:25items:26- const: cfg27- const: sram2829clocks:30items:31- description: mux for audio dsp clock32- description: 26M clock33- description: mux for audio dsp local bus34- description: default audio dsp local bus clock source35- description: clock gate for audio dsp clock36- description: mux for audio dsp access external bus3738clock-names:39items:40- const: adsp_sel41- const: clk26m_ck42- const: audio_local_bus43- const: mainpll_d7_d244- const: scp_adsp_audiodsp45- const: audio_h4647power-domains:48maxItems: 14950mboxes:51items:52- description: mailbox for receiving audio DSP requests.53- description: mailbox for transmitting requests to audio DSP.5455mbox-names:56items:57- const: rx58- const: tx5960memory-region:61items:62- description: dma buffer between host and DSP.63- description: DSP system memory.6465required:66- compatible67- reg68- reg-names69- clocks70- clock-names71- memory-region72- power-domains73- mbox-names74- mboxes7576additionalProperties: false7778examples:79- |80#include <dt-bindings/interrupt-controller/arm-gic.h>81#include <dt-bindings/interrupt-controller/irq.h>82dsp@10803000 {83compatible = "mediatek,mt8195-dsp";84reg = <0x10803000 0x1000>,85<0x10840000 0x40000>;86reg-names = "cfg", "sram";87clocks = <&topckgen 10>, //CLK_TOP_ADSP88<&clk26m>,89<&topckgen 107>, //CLK_TOP_AUDIO_LOCAL_BUS90<&topckgen 136>, //CLK_TOP_MAINPLL_D7_D291<&scp_adsp 0>, //CLK_SCP_ADSP_AUDIODSP92<&topckgen 34>; //CLK_TOP_AUDIO_H93clock-names = "adsp_sel",94"clk26m_ck",95"audio_local_bus",96"mainpll_d7_d2",97"scp_adsp_audiodsp",98"audio_h";99memory-region = <&adsp_dma_mem_reserved>,100<&adsp_mem_reserved>;101power-domains = <&spm 6>; //MT8195_POWER_DOMAIN_ADSP102mbox-names = "rx", "tx";103mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>;104};105106107