altr,fpga-passive-serial.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/fpga/altr,fpga-passive-serial.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Altera Passive Serial SPI FPGA Manager

maintainers:
  - Fabio Estevam <[e-mail]>

description: |
  Altera FPGAs support a method of loading the bitstream over what is
  referred to as "passive serial".
  The passive serial link is not technically SPI, and might require extra
  circuits in order to play nicely with other SPI slaves on the same bus.

  See https://www.altera.com/literature/hb/cyc/cyc_c51013.pdf

allOf:
  - $ref: /schemas/spi/spi-peripheral-props.yaml#

properties:
  compatible:
    enum:
      - altr,fpga-passive-serial
      - altr,fpga-arria10-passive-serial

  spi-max-frequency:
    maximum: 20000000

  reg:
    maxItems: 1

  nconfig-gpios:
    description:
      Config pin (referred to as nCONFIG in the manual).
    maxItems: 1

  nstat-gpios:
    description:
      Status pin (referred to as nSTATUS in the manual).
    maxItems: 1

  confd-gpios:
    description:
      confd pin (referred to as CONF_DONE in the manual)
    maxItems: 1

required:
  - compatible
  - reg
  - nconfig-gpios
  - nstat-gpios

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>

    spi {
      #address-cells = <1>;
      #size-cells = <0>;

      fpga@0 {
        compatible = "altr,fpga-passive-serial";
        reg = <0>;
        nconfig-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>;
        nstat-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
        confd-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
      };
    };
...