Path: blob/master/Documentation/devicetree/bindings/fpga/altr,freeze-bridge-controller.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)1%YAML 1.22---3$id: http://devicetree.org/schemas/fpga/altr,freeze-bridge-controller.yaml#4$schema: http://devicetree.org/meta-schemas/core.yaml#56title: Altera Freeze Bridge Controller78description:9The Altera Freeze Bridge Controller manages one or more freeze bridges.10The controller can freeze/disable the bridges which prevents signal11changes from passing through the bridge. The controller can also12unfreeze/enable the bridges which allows traffic to pass through the bridge13normally.1415maintainers:16- Xu Yilun <yilun.xu@intel.com>1718allOf:19- $ref: fpga-bridge.yaml#2021properties:22compatible:23const: altr,freeze-bridge-controller2425reg:26maxItems: 12728required:29- compatible30- reg3132unevaluatedProperties: false3334examples:35- |36fpga-bridge@100000450 {37compatible = "altr,freeze-bridge-controller";38reg = <0x1000 0x10>;39bridge-enable = <0>;40};414243