Path: blob/master/Documentation/devicetree/bindings/fpga/altr,socfpga-hps2fpga-bridge.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)1%YAML 1.22---3$id: http://devicetree.org/schemas/fpga/altr,socfpga-hps2fpga-bridge.yaml#4$schema: http://devicetree.org/meta-schemas/core.yaml#56title: Altera FPGA/HPS Bridge78maintainers:9- Xu Yilun <yilun.xu@intel.com>1011allOf:12- $ref: fpga-bridge.yaml#1314properties:15compatible:16enum:17- altr,socfpga-lwhps2fpga-bridge18- altr,socfpga-hps2fpga-bridge19- altr,socfpga-fpga2hps-bridge2021reg:22maxItems: 12324resets:25maxItems: 12627clocks:28maxItems: 12930required:31- compatible32- reg33- clocks34- resets3536unevaluatedProperties: false3738examples:39- |40#include <dt-bindings/reset/altr,rst-mgr.h>4142fpga-bridge@ff400000 {43compatible = "altr,socfpga-lwhps2fpga-bridge";44reg = <0xff400000 0x100000>;45bridge-enable = <0>;46clocks = <&l4_main_clk>;47resets = <&rst LWHPS2FPGA_RESET>;48};495051