Path: blob/master/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)1%YAML 1.22---3$id: http://devicetree.org/schemas/fuse/nvidia,tegra20-fuse.yaml#4$schema: http://devicetree.org/meta-schemas/core.yaml#56title: NVIDIA Tegra FUSE block78maintainers:9- Thierry Reding <thierry.reding@gmail.com>10- Jon Hunter <jonathanh@nvidia.com>1112properties:13compatible:14oneOf:15- enum:16- nvidia,tegra20-efuse17- nvidia,tegra30-efuse18- nvidia,tegra114-efuse19- nvidia,tegra124-efuse20- nvidia,tegra210-efuse21- nvidia,tegra186-efuse22- nvidia,tegra194-efuse23- nvidia,tegra234-efuse2425- items:26- const: nvidia,tegra132-efuse27- const: nvidia,tegra124-efuse2829reg:30maxItems: 13132clocks:33maxItems: 13435clock-names:36items:37- const: fuse3839resets:40maxItems: 14142reset-names:43items:44- const: fuse4546operating-points-v2: true4748power-domains:49items:50- description: phandle to the core power domain5152additionalProperties: false5354required:55- compatible56- reg57- clocks58- clock-names5960if:61properties:62compatible:63contains:64enum:65- nvidia,tegra20-efuse66- nvidia,tegra30-efuse67- nvidia,tegra114-efuse68- nvidia,tegra124-efuse69- nvidia,tegra132-efuse70- nvidia,tegra210-efuse71then:72required:73- resets74- reset-names7576examples:77- |78#include <dt-bindings/clock/tegra20-car.h>7980fuse@7000f800 {81compatible = "nvidia,tegra20-efuse";82reg = <0x7000f800 0x400>;83clocks = <&tegra_car TEGRA20_CLK_FUSE>;84clock-names = "fuse";85resets = <&tegra_car 39>;86reset-names = "fuse";87};888990