Path: blob/master/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)1%YAML 1.22---3$id: http://devicetree.org/schemas/gpio/aspeed,sgpio.yaml#4$schema: http://devicetree.org/meta-schemas/core.yaml#56title: Aspeed SGPIO controller78maintainers:9- Andrew Jeffery <andrew@aj.id.au>1011description:12This SGPIO controller is for ASPEED AST2400, AST2500 and AST2600 SoC,13AST2600 have two sgpio master one with 128 pins another one with 80 pins,14AST2500/AST2400 have one sgpio master with 80 pins. Each of the Serial15GPIO pins can be programmed to support the following options16- Support interrupt option for each input port and various interrupt17sensitivity option (level-high, level-low, edge-high, edge-low)18- Support reset tolerance option for each output port19- Directly connected to APB bus and its shift clock is from APB bus clock20divided by a programmable value.21- Co-work with external signal-chained TTL components (74LV165/74LV595)2223properties:24compatible:25enum:26- aspeed,ast2400-sgpio27- aspeed,ast2500-sgpio28- aspeed,ast2600-sgpiom2930reg:31maxItems: 13233gpio-controller: true3435# Each SGPIO is represented as a pair of input and output GPIOs36gpio-line-names:37minItems: 16038maxItems: 2563940'#gpio-cells':41const: 24243interrupts:44maxItems: 14546interrupt-controller: true4748'#interrupt-cells':49const: 25051clocks:52maxItems: 15354ngpios: true5556bus-frequency: true5758required:59- compatible60- reg61- gpio-controller62- '#gpio-cells'63- interrupts64- interrupt-controller65- '#interrupt-cells'66- ngpios67- clocks68- bus-frequency6970additionalProperties: false7172examples:73- |74#include <dt-bindings/clock/aspeed-clock.h>75sgpio: sgpio@1e780200 {76#gpio-cells = <2>;77compatible = "aspeed,ast2500-sgpio";78gpio-controller;79interrupts = <40>;80reg = <0x1e780200 0x0100>;81clocks = <&syscon ASPEED_CLK_APB>;82interrupt-controller;83#interrupt-cells = <2>;84ngpios = <80>;85bus-frequency = <12000000>;86};878889