Path: blob/master/Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)1%YAML 1.22---3$id: http://devicetree.org/schemas/gpio/brcm,brcmstb-gpio.yaml#4$schema: http://devicetree.org/meta-schemas/core.yaml#56title: Broadcom STB "UPG GIO" GPIO controller78description: >9The controller's registers are organized as sets of eight 32-bit10registers with each set controlling a bank of up to 32 pins. A single11interrupt is shared for all of the banks handled by the controller.1213maintainers:14- Doug Berger <opendmb@gmail.com>15- Florian Fainelli <f.fainelli@gmail.com>1617properties:18compatible:19items:20- enum:21- brcm,bcm7445-gpio22- const: brcm,brcmstb-gpio2324reg:25maxItems: 126description: >27Define the base and range of the I/O address space containing28the brcmstb GPIO controller registers2930"#gpio-cells":31const: 232description: >33The first cell is the pin number (within the controller's34pin space), and the second is used for the following:35bit[0]: polarity (0 for active-high, 1 for active-low)3637gpio-controller: true3839brcm,gpio-bank-widths:40$ref: /schemas/types.yaml#/definitions/uint32-array41description: >42Number of GPIO lines for each bank. Number of elements must43correspond to number of banks suggested by the 'reg' property.4445interrupts:46maxItems: 147description: >48The interrupt shared by all GPIO lines for this controller.4950"#interrupt-cells":51const: 252description: |53The first cell is the GPIO number, the second should specify54flags. The following subset of flags is supported:55- bits[3:0] trigger type and level flags561 = low-to-high edge triggered572 = high-to-low edge triggered584 = active high level-sensitive598 = active low level-sensitive60Valid combinations are 1, 2, 3, 4, 8.6162interrupt-controller: true6364gpio-ranges: true6566gpio-line-names:67minItems: 168maxItems: 1286970wakeup-source:71type: boolean72description: >73GPIOs for this controller can be used as a wakeup source7475required:76- compatible77- reg78- gpio-controller79- "#gpio-cells"80- brcm,gpio-bank-widths8182additionalProperties: false8384examples:85- |86upg_gio: gpio@f040a700 {87#gpio-cells = <2>;88#interrupt-cells = <2>;89compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";90gpio-controller;91interrupt-controller;92reg = <0xf040a700 0x80>;93interrupt-parent = <&irq0_intc>;94interrupts = <0x6>;95brcm,gpio-bank-widths = <32 32 32 24>;96gpio-ranges = <&pinctrl 0 0 120>;97};9899upg_gio_aon: gpio@f04172c0 {100#gpio-cells = <2>;101#interrupt-cells = <2>;102compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";103gpio-controller;104interrupt-controller;105reg = <0xf04172c0 0x40>;106interrupt-parent = <&irq0_aon_intc>;107interrupts = <0x6>;108wakeup-source;109brcm,gpio-bank-widths = <18 4>;110};111112113