Path: blob/master/Documentation/devicetree/bindings/gpio/cavium,octeon-3860-gpio.yaml
26308 views
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)1%YAML 1.22---3$id: http://devicetree.org/schemas/cavium,octeon-3860-gpio.yaml#4$schema: http://devicetree.org/meta-schemas/core.yaml#56title: Cavium Octeon 3860 GPIO controller78maintainers:9- Bartosz Golaszewski <brgl@bgdev.pl>1011properties:12compatible:13const: cavium,octeon-3860-gpio1415reg:16maxItems: 11718gpio-controller: true1920'#gpio-cells':21const: 22223interrupt-controller: true2425'#interrupt-cells':26const: 22728interrupts:29maxItems: 163031required:32- compatible33- reg34- gpio-controller35- '#gpio-cells'36- interrupt-controller37- '#interrupt-cells'38- interrupts3940additionalProperties: false4142examples:43- |44bus {45#address-cells = <2>;46#size-cells = <2>;4748gpio@1070000000800 {49compatible = "cavium,octeon-3860-gpio";50reg = <0x10700 0x00000800 0x0 0x100>;51gpio-controller;52#gpio-cells = <2>;53interrupt-controller;54#interrupt-cells = <2>;55/* The GPIO pin connect to 16 consecutive CUI bits */56interrupts = <0 16>, <0 17>, <0 18>, <0 19>,57<0 20>, <0 21>, <0 22>, <0 23>,58<0 24>, <0 25>, <0 26>, <0 27>,59<0 28>, <0 29>, <0 30>, <0 31>;60};61};626364