Path: blob/master/Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)1%YAML 1.22---3$id: http://devicetree.org/schemas/gpio/fairchild,74hc595.yaml#4$schema: http://devicetree.org/meta-schemas/core.yaml#56title: Generic 8-bit shift register78description: |9NOTE: These chips nominally don't have a chip select pin. They do however10have a rising-edge triggered latch clock (or storage register clock) pin,11which behaves like an active-low chip select.1213After the bits are shifted into the shift register, CS# is driven high, which14the 74HC595 sees as a rising edge on the latch clock that results in a15transfer of the bits from the shift register to the storage register and thus16to the output pins.17_ _ _ _18shift clock ____| |_| |_..._| |_| |_________1920latch clock * trigger21___ ________22chip select# |___________________|232425maintainers:26- Maxime Ripard <mripard@kernel.org>2728properties:29compatible:30enum:31- fairchild,74hc59532- nxp,74lvc5943334reg:35maxItems: 13637gpio-controller: true3839'#gpio-cells':40description:41The second cell is only used to specify the GPIO polarity.42const: 24344registers-number:45$ref: /schemas/types.yaml#/definitions/uint3246description: Number of daisy-chained shift registers4748enable-gpios:49description: GPIO connected to the OE (Output Enable) pin.50maxItems: 15152patternProperties:53"^(hog-[0-9]+|.+-hog(-[0-9]+)?)$":54type: object55required:56- gpio-hog5758required:59- compatible60- reg61- gpio-controller62- '#gpio-cells'63- registers-number6465allOf:66- $ref: /schemas/spi/spi-peripheral-props.yaml#6768unevaluatedProperties: false6970examples:71- |72spi {73#address-cells = <1>;74#size-cells = <0>;7576gpio5@0 {77compatible = "fairchild,74hc595";78reg = <0>;79gpio-controller;80#gpio-cells = <2>;81registers-number = <4>;82spi-max-frequency = <100000>;83};84};858687