Path: blob/master/Documentation/devicetree/bindings/gpio/gpio-davinci.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)1%YAML 1.22---3$id: http://devicetree.org/schemas/gpio/gpio-davinci.yaml#4$schema: http://devicetree.org/meta-schemas/core.yaml#56title: GPIO controller for Davinci and keystone devices78maintainers:9- Keerthy <j-keerthy@ti.com>1011properties:12compatible:13oneOf:14- items:15- enum:16- ti,k2g-gpio17- ti,am654-gpio18- ti,j721e-gpio19- ti,am64-gpio20- const: ti,keystone-gpio2122- items:23- enum:24- ti,dm6441-gpio25- ti,keystone-gpio2627reg:28maxItems: 12930gpio-controller: true3132gpio-ranges: true3334gpio-reserved-ranges: true3536gpio-line-names:37description: strings describing the names of each gpio line.38minItems: 139maxItems: 1444041"#gpio-cells":42const: 243description:44first cell is the pin number and second cell is used to specify optional parameters (unused).4546interrupts:47description:48The interrupts are specified as per the interrupt parent. Only banked49or unbanked IRQs are supported at a time. If the interrupts are50banked then provide list of interrupts corresponding to each bank, else51provide the list of interrupts for each gpio.52minItems: 153maxItems: 1005455ti,ngpio:56$ref: /schemas/types.yaml#/definitions/uint3257description: The number of GPIO pins supported consecutively.58minimum: 15960ti,davinci-gpio-unbanked:61$ref: /schemas/types.yaml#/definitions/uint3262description: The number of GPIOs that have an individual interrupt line to processor.63minimum: 06465clocks:66maxItems: 16768clock-names:69const: gpio7071interrupt-controller: true7273power-domains:74maxItems: 17576"#interrupt-cells":77const: 27879patternProperties:80"^(.+-hog(-[0-9]+)?)$":81type: object8283required:84- gpio-hog8586required:87- compatible88- reg89- gpio-controller90- "#gpio-cells"91- interrupts92- ti,ngpio93- ti,davinci-gpio-unbanked94- clocks95- clock-names9697additionalProperties: false9899examples:100- |101#include<dt-bindings/interrupt-controller/arm-gic.h>102103gpio0: gpio@2603000 {104compatible = "ti,k2g-gpio", "ti,keystone-gpio";105reg = <0x02603000 0x100>;106gpio-controller;107#gpio-cells = <2>;108interrupts = <GIC_SPI 432 IRQ_TYPE_EDGE_RISING>,109<GIC_SPI 433 IRQ_TYPE_EDGE_RISING>,110<GIC_SPI 434 IRQ_TYPE_EDGE_RISING>,111<GIC_SPI 435 IRQ_TYPE_EDGE_RISING>,112<GIC_SPI 436 IRQ_TYPE_EDGE_RISING>,113<GIC_SPI 437 IRQ_TYPE_EDGE_RISING>,114<GIC_SPI 438 IRQ_TYPE_EDGE_RISING>,115<GIC_SPI 439 IRQ_TYPE_EDGE_RISING>,116<GIC_SPI 440 IRQ_TYPE_EDGE_RISING>;117interrupt-controller;118#interrupt-cells = <2>;119ti,ngpio = <144>;120ti,davinci-gpio-unbanked = <0>;121clocks = <&k2g_clks 0x001b 0x0>;122clock-names = "gpio";123};124125- |126#include<dt-bindings/interrupt-controller/arm-gic.h>127128gpio1: gpio@260bf00 {129compatible = "ti,keystone-gpio";130reg = <0x0260bf00 0x100>;131gpio-controller;132#gpio-cells = <2>;133/* HW Interrupts mapped to GPIO pins */134interrupts = <GIC_SPI 120 IRQ_TYPE_EDGE_RISING>,135<GIC_SPI 121 IRQ_TYPE_EDGE_RISING>,136<GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,137<GIC_SPI 123 IRQ_TYPE_EDGE_RISING>,138<GIC_SPI 124 IRQ_TYPE_EDGE_RISING>,139<GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,140<GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,141<GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,142<GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,143<GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,144<GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,145<GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,146<GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,147<GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,148<GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,149<GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,150<GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,151<GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,152<GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,153<GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,154<GIC_SPI 140 IRQ_TYPE_EDGE_RISING>,155<GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,156<GIC_SPI 142 IRQ_TYPE_EDGE_RISING>,157<GIC_SPI 143 IRQ_TYPE_EDGE_RISING>,158<GIC_SPI 144 IRQ_TYPE_EDGE_RISING>,159<GIC_SPI 145 IRQ_TYPE_EDGE_RISING>,160<GIC_SPI 146 IRQ_TYPE_EDGE_RISING>,161<GIC_SPI 147 IRQ_TYPE_EDGE_RISING>,162<GIC_SPI 148 IRQ_TYPE_EDGE_RISING>,163<GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,164<GIC_SPI 150 IRQ_TYPE_EDGE_RISING>,165<GIC_SPI 151 IRQ_TYPE_EDGE_RISING>;166clocks = <&clkgpio>;167clock-names = "gpio";168ti,ngpio = <32>;169ti,davinci-gpio-unbanked = <32>;170};171172- |173wkup_gpio0: gpio0@42110000 {174compatible = "ti,am654-gpio", "ti,keystone-gpio";175reg = <0x42110000 0x100>;176gpio-controller;177#gpio-cells = <2>;178interrupt-parent = <&intr_wkup_gpio>;179interrupts = <60>, <61>, <62>, <63>;180interrupt-controller;181#interrupt-cells = <2>;182ti,ngpio = <56>;183ti,davinci-gpio-unbanked = <0>;184clocks = <&k3_clks 59 0>;185clock-names = "gpio";186};187188189