Path: blob/master/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvjpg.yaml
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)1%YAML 1.22---3$id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvjpg.yaml#4$schema: http://devicetree.org/meta-schemas/core.yaml#56title: NVIDIA Tegra NVJPG78description: |9NVJPG is the hardware JPEG decoder and encoder present on NVIDIA Tegra21010and newer chips. It is located on the Host1x bus and typically programmed11through Host1x channels.1213maintainers:14- Thierry Reding <treding@gmail.com>15- Mikko Perttunen <mperttunen@nvidia.com>1617properties:18$nodename:19pattern: "^nvjpg@[0-9a-f]*$"2021compatible:22enum:23- nvidia,tegra210-nvjpg24- nvidia,tegra186-nvjpg25- nvidia,tegra194-nvjpg2627reg:28maxItems: 12930clocks:31maxItems: 13233clock-names:34items:35- const: nvjpg3637resets:38maxItems: 13940reset-names:41items:42- const: nvjpg4344power-domains:45maxItems: 14647iommus:48maxItems: 14950dma-coherent: true5152interconnects:53items:54- description: DMA read memory client55- description: DMA write memory client5657interconnect-names:58items:59- const: dma-mem60- const: write6162required:63- compatible64- reg65- clocks66- clock-names67- resets68- reset-names69- power-domains7071additionalProperties: false7273examples:74- |75#include <dt-bindings/clock/tegra186-clock.h>76#include <dt-bindings/memory/tegra186-mc.h>77#include <dt-bindings/power/tegra186-powergate.h>78#include <dt-bindings/reset/tegra186-reset.h>7980nvjpg@15380000 {81compatible = "nvidia,tegra186-nvjpg";82reg = <0x15380000 0x40000>;83clocks = <&bpmp TEGRA186_CLK_NVJPG>;84clock-names = "nvjpg";85resets = <&bpmp TEGRA186_RESET_NVJPG>;86reset-names = "nvjpg";8788power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVJPG>;89interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVJPGSRD &emc>,90<&mc TEGRA186_MEMORY_CLIENT_NVJPGSWR &emc>;91interconnect-names = "dma-mem", "write";92iommus = <&smmu TEGRA186_SID_NVJPG>;93};949596