Path: blob/master/Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)1%YAML 1.22---3$id: http://devicetree.org/schemas/i2c/aspeed,i2c.yaml#4$schema: http://devicetree.org/meta-schemas/core.yaml#56title: ASPEED I2C on the AST24XX, AST25XX, and AST26XX SoCs78maintainers:9- Rayn Chen <rayn_chen@aspeedtech.com>1011allOf:12- $ref: /schemas/i2c/i2c-controller.yaml#1314properties:15compatible:16enum:17- aspeed,ast2400-i2c-bus18- aspeed,ast2500-i2c-bus19- aspeed,ast2600-i2c-bus2021reg:22minItems: 123items:24- description: address offset and range of bus25- description: address offset and range of bus buffer2627interrupts:28maxItems: 12930clocks:31maxItems: 132description:33root clock of bus, should reference the APB34clock in the second cell3536resets:37maxItems: 13839bus-frequency:40minimum: 50041maximum: 400000042default: 10000043description: frequency of the bus clock in Hz defaults to 100 kHz when not44specified4546required:47- reg48- compatible49- clocks50- resets5152unevaluatedProperties: false5354examples:55- |56#include <dt-bindings/clock/aspeed-clock.h>57i2c@40 {58#address-cells = <1>;59#size-cells = <0>;60compatible = "aspeed,ast2500-i2c-bus";61reg = <0x40 0x40>;62clocks = <&syscon ASPEED_CLK_APB>;63resets = <&syscon ASPEED_RESET_I2C>;64bus-frequency = <100000>;65interrupts = <0>;66interrupt-parent = <&i2c_ic>;67};686970