Path: blob/master/Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)1%YAML 1.22---3$id: http://devicetree.org/schemas/i2c/cdns,i2c-r1p10.yaml#4$schema: http://devicetree.org/meta-schemas/core.yaml#56title: Cadence I2C controller78maintainers:9- Michal Simek <michal.simek@amd.com>1011allOf:12- $ref: /schemas/i2c/i2c-controller.yaml#1314properties:15compatible:16enum:17- cdns,i2c-r1p10 # cadence i2c controller version 1.018- cdns,i2c-r1p14 # cadence i2c controller version 1.41920reg:21maxItems: 12223clocks:24minItems: 12526resets:27maxItems: 12829interrupts:30maxItems: 13132clock-frequency:33minimum: 134maximum: 40000035description: |36Desired operating frequency, in Hz, of the bus.3738clock-name:39const: pclk40description: |41Input clock name.4243fifo-depth:44description:45Size of the data FIFO in bytes.46$ref: /schemas/types.yaml#/definitions/uint3247default: 1648enum: [2, 4, 8, 16, 32, 64, 128, 256]4950power-domains:51maxItems: 15253required:54- compatible55- reg56- clocks57- interrupts5859unevaluatedProperties: false6061examples:62- |63#include <dt-bindings/interrupt-controller/arm-gic.h>64i2c@e0004000 {65compatible = "cdns,i2c-r1p10";66clocks = <&clkc 38>;67resets = <&rstc 288>;68interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;69reg = <0xe0004000 0x1000>;70clock-frequency = <400000>;71#address-cells = <1>;72#size-cells = <0>;73fifo-depth = <8>;74};757677