Path: blob/master/Documentation/devicetree/bindings/i2c/hpe,gxp-i2c.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)1%YAML 1.22---3$id: http://devicetree.org/schemas/i2c/hpe,gxp-i2c.yaml#4$schema: http://devicetree.org/meta-schemas/core.yaml#56title: HPE GXP SoC I2C Controller78maintainers:9- Nick Hawkins <nick.hawkins@hpe.com>1011allOf:12- $ref: /schemas/i2c/i2c-controller.yaml#1314properties:15compatible:16const: hpe,gxp-i2c1718reg:19maxItems: 12021interrupts:22maxItems: 12324clock-frequency:25default: 1000002627hpe,sysreg:28$ref: /schemas/types.yaml#/definitions/phandle29description:30Phandle to the global status and enable interrupt registers shared31between each I2C engine controller instance. It enables the I2C32engine controller to act as both a master or slave by being able to33arm and respond to interrupts from its engine. Each bit in the34registers represent the respective bit position.3536required:37- compatible38- reg39- interrupts4041unevaluatedProperties: false4243examples:44- |45i2c@2600 {46compatible = "hpe,gxp-i2c";47reg = <0x2500 0x70>;48interrupts = <9>;49#address-cells = <1>;50#size-cells = <0>;51hpe,sysreg = <&sysreg_system_controller>;52clock-frequency = <10000>;5354eeprom@50 {55compatible = "atmel,24c128";56reg = <0x50>;57};58};596061