Path: blob/master/Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)1%YAML 1.22---3$id: http://devicetree.org/schemas/iio/adc/adi,ad4134.yaml#4$schema: http://devicetree.org/meta-schemas/core.yaml#56title: Analog Devices AD4134 ADC78maintainers:9- Marcelo Schmitt <marcelo.schmitt@analog.com>1011description: |12The AD4134 is a quad channel, low noise, simultaneous sampling, precision13analog-to-digital converter (ADC).14Specifications can be found at:15https://www.analog.com/media/en/technical-documentation/data-sheets/ad4134.pdf1617$ref: /schemas/spi/spi-peripheral-props.yaml#1819properties:20compatible:21enum:22- adi,ad41342324reg:25maxItems: 12627spi-max-frequency:28maximum: 500000002930avdd5-supply:31description: A 5V supply that powers the chip's analog circuitry.3233dvdd5-supply:34description: A 5V supply that powers the chip's digital circuitry.3536iovdd-supply:37description:38A 1.8V supply that sets the logic levels for the digital interface pins.3940refin-supply:41description:42A 4.096V or 5V supply that serves as reference for ADC conversions.4344avdd1v8-supply:45description: A 1.8V supply used by the analog circuitry.4647dvdd1v8-supply:48description: A 1.8V supply used by the digital circuitry.4950clkvdd-supply:51description: A 1.8V supply for the chip's clock management circuit.5253ldoin-supply:54description:55A 2.6V to 5.5V supply that generates 1.8V for AVDD1V8, DVDD1V8, and CLKVDD56pins.5758clocks:59maxItems: 160description:61Required external clock source. Can specify either a crystal or CMOS clock62source. If an external crystal is set, connect the CLKSEL pin to IOVDD.63Otherwise, connect the CLKSEL pin to IOGND and the external CMOS clock64signal to the XTAL2/CLKIN pin.6566clock-names:67enum:68- xtal69- clkin70default: clkin7172'#clock-cells':73const: 07475clock-output-names:76maxItems: 17778regulators:79type: object80description:81list of regulators provided by this controller.8283properties:84vcm-output:85$ref: /schemas/regulator/regulator.yaml#86type: object87unevaluatedProperties: false8889additionalProperties: false9091reset-gpios:92maxItems: 19394powerdown-gpios:95description:96Active low GPIO connected to the /PDN pin. Forces the device into full97power-down mode when brought low. Pull this input to IOVDD for normal98operation.99maxItems: 1100101odr-gpios:102description:103GPIO connected to ODR pin. Used to sample ADC data in minimum I/O mode.104maxItems: 1105106adi,asrc-mode:107$ref: /schemas/types.yaml#/definitions/string108description:109Asynchronous Sample Rate Converter (ASRC) operation mode control input.110Describes whether the MODE pin is set to a high level (for master mode111operation) or to a low level (for slave mode operation).112enum: [ high, low ]113default: low114115adi,dclkio:116description:117DCLK pin I/O direction control for when the device operates in Pin Control118Slave Mode or in SPI Control Mode. Describes if DEC0/DCLKIO pin is at a119high level (which configures DCLK as an output) or to set to a low level120(configuring DCLK for input).121enum: [ out, in ]122default: in123124adi,dclkmode:125description:126DCLK mode control for when the device operates in Pin Control Slave Mode127or in SPI Control Mode. Describes whether the DEC1/DCLKMODE pin is set to128a high level (configuring the DCLK to operate in free running mode) or129to a low level (to configure DCLK to operate in gated mode).130enum: [ free-running, gated ]131default: gated132133required:134- compatible135- reg136- avdd5-supply137- dvdd5-supply138- iovdd-supply139- refin-supply140- clocks141- clock-names142143oneOf:144- required:145- ldoin-supply146- required:147- avdd1v8-supply148- dvdd1v8-supply149- clkvdd-supply150151unevaluatedProperties: false152153examples:154- |155#include <dt-bindings/gpio/gpio.h>156157spi {158#address-cells = <1>;159#size-cells = <0>;160161adc@0 {162compatible = "adi,ad4134";163reg = <0>;164165spi-max-frequency = <1000000>;166167reset-gpios = <&gpio0 86 GPIO_ACTIVE_LOW>;168odr-gpios = <&gpio0 87 GPIO_ACTIVE_HIGH>;169powerdown-gpios = <&gpio0 88 GPIO_ACTIVE_LOW>;170171clocks = <&sys_clk>;172clock-names = "clkin";173174avdd5-supply = <&avdd5>;175dvdd5-supply = <&dvdd5>;176iovdd-supply = <&iovdd>;177refin-supply = <&refin>;178avdd1v8-supply = <&avdd1v8>;179dvdd1v8-supply = <&dvdd1v8>;180clkvdd-supply = <&clkvdd>;181182regulators {183vcm_reg: vcm-output {184regulator-name = "ad4134-vcm";185};186};187188};189};190...191192193