Path: blob/master/Documentation/devicetree/bindings/iio/adc/adi,ad7191.yaml
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)1# Copyright 2025 Analog Devices Inc.2%YAML 1.23---4$id: http://devicetree.org/schemas/iio/adc/adi,ad7191.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#67title: Analog Devices AD7191 ADC89maintainers:10- Alisa-Dariana Roman <alisa.roman@analog.com>1112description: |13Bindings for the Analog Devices AD7191 ADC device. Datasheet can be14found here:15https://www.analog.com/media/en/technical-documentation/data-sheets/AD7191.pdf16The device's PDOWN pin must be connected to the SPI controller's chip select17pin.1819properties:20compatible:21enum:22- adi,ad71912324reg:25maxItems: 12627spi-cpol: true2829spi-cpha: true3031clocks:32maxItems: 133description:34Must be present when CLKSEL pin is tied HIGH to select external clock35source (either a crystal between MCLK1 and MCLK2 pins, or a36CMOS-compatible clock driving MCLK2 pin). Must be absent when CLKSEL pin37is tied LOW to use the internal 4.92MHz clock.3839interrupts:40maxItems: 14142avdd-supply:43description: AVdd voltage supply4445dvdd-supply:46description: DVdd voltage supply4748vref-supply:49description: Vref voltage supply5051odr-gpios:52description:53ODR1 and ODR2 pins for output data rate selection. Should be defined if54adi,odr-value is absent.55minItems: 256maxItems: 25758adi,odr-value:59$ref: /schemas/types.yaml#/definitions/uint3260description: |61Should be present if ODR pins are pin-strapped. Possible values:62120 Hz (ODR1=0, ODR2=0)6360 Hz (ODR1=0, ODR2=1)6450 Hz (ODR1=1, ODR2=0)6510 Hz (ODR1=1, ODR2=1)66If defined, odr-gpios must be absent.67enum: [120, 60, 50, 10]6869pga-gpios:70description:71PGA1 and PGA2 pins for gain selection. Should be defined if adi,pga-value72is absent.73minItems: 274maxItems: 27576adi,pga-value:77$ref: /schemas/types.yaml#/definitions/uint3278description: |79Should be present if PGA pins are pin-strapped. Possible values:80Gain 1 (PGA1=0, PGA2=0)81Gain 8 (PGA1=0, PGA2=1)82Gain 64 (PGA1=1, PGA2=0)83Gain 128 (PGA1=1, PGA2=1)84If defined, pga-gpios must be absent.85enum: [1, 8, 64, 128]8687temp-gpios:88description: TEMP pin for temperature sensor enable.89maxItems: 19091chan-gpios:92description: CHAN pin for input channel selection.93maxItems: 19495required:96- compatible97- reg98- interrupts99- avdd-supply100- dvdd-supply101- vref-supply102- spi-cpol103- spi-cpha104- temp-gpios105- chan-gpios106107allOf:108- $ref: /schemas/spi/spi-peripheral-props.yaml#109- oneOf:110- required:111- adi,odr-value112- required:113- odr-gpios114- oneOf:115- required:116- adi,pga-value117- required:118- pga-gpios119120unevaluatedProperties: false121122examples:123- |124#include <dt-bindings/gpio/gpio.h>125#include <dt-bindings/interrupt-controller/irq.h>126127spi {128#address-cells = <1>;129#size-cells = <0>;130131adc@0 {132compatible = "adi,ad7191";133reg = <0>;134spi-max-frequency = <1000000>;135spi-cpol;136spi-cpha;137clocks = <&ad7191_mclk>;138interrupts = <25 IRQ_TYPE_EDGE_FALLING>;139interrupt-parent = <&gpio>;140avdd-supply = <&avdd>;141dvdd-supply = <&dvdd>;142vref-supply = <&vref>;143adi,pga-value = <1>;144odr-gpios = <&gpio 23 GPIO_ACTIVE_HIGH>, <&gpio 24 GPIO_ACTIVE_HIGH>;145temp-gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;146chan-gpios = <&gpio 27 GPIO_ACTIVE_HIGH>;147};148};149150151