Path: blob/master/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)1# Copyright 2019 Analog Devices Inc.2%YAML 1.23---4$id: http://devicetree.org/schemas/iio/adc/adi,ad7192.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#67title: Analog Devices AD7192 ADC device driver89maintainers:10- Michael Hennerich <michael.hennerich@analog.com>1112description: |13Bindings for the Analog Devices AD7192 ADC device. Datasheet can be14found here:15https://www.analog.com/media/en/technical-documentation/data-sheets/AD7192.pdf1617properties:18compatible:19enum:20- adi,ad719021- adi,ad719222- adi,ad719323- adi,ad719424- adi,ad71952526"#address-cells":27const: 12829"#size-cells":30const: 03132reg:33maxItems: 13435spi-cpol: true3637spi-cpha: true3839clocks:40maxItems: 141description:42Optionally, either a crystal can be attached externally between MCLK1 and43MCLK2 pins, or an external CMOS-compatible clock can drive the MCLK244pin. If absent, internal 4.92MHz clock is used, which can be made45available on MCLK2 pin.4647clock-names:48enum:49- xtal50- mclk5152"#clock-cells":53const: 054description:55If present when internal clock is used, configured as clock provider.5657interrupts:58maxItems: 15960aincom-supply:61description: |62AINCOM voltage supply. Analog inputs AINx are referenced to this input63when configured for pseudo-differential operation.6465dvdd-supply:66description: DVdd voltage supply6768avdd-supply:69description: AVdd voltage supply7071vref-supply:72description: VRef voltage supply7374adi,rejection-60-Hz-enable:75description: |76This bit enables a notch at 60 Hz when the first notch of the sinc77filter is at 50 Hz. When REJ60 is set, a filter notch is placed at7860 Hz when the sinc filter first notch is at 50 Hz. This allows79simultaneous 50 Hz/ 60 Hz rejection.80type: boolean8182adi,refin2-pins-enable:83description: |84External reference applied between the P1/REFIN2(+) and P0/REFIN2(−) pins.85type: boolean8687adi,buffer-enable:88description: |89Enables the buffer on the analog inputs. If cleared, the analog inputs90are unbuffered, lowering the power consumption of the device. If this91bit is set, the analog inputs are buffered, allowing the user to place92source impedances on the front end without contributing gain errors to93the system.94type: boolean9596adi,burnout-currents-enable:97description: |98When this bit is set to 1, the 500 nA current sources in the signal99path are enabled. When BURN = 0, the burnout currents are disabled.100The burnout currents can be enabled only when the buffer is active101and when chop is disabled.102type: boolean103104bipolar:105description: see Documentation/devicetree/bindings/iio/adc/adc.yaml106type: boolean107108rdy-gpios:109description:110GPIO reading the R̅D̅Y̅ line. Having such a GPIO is technically optional but111highly recommended because DOUT/R̅D̅Y̅ toggles during SPI transfers (in its112DOUT aka MISO role) and so usually triggers a spurious interrupt. The113distinction between such a spurious event and a real one can only be done114by reading such a GPIO. (There is a register telling the same115information, but accessing that one needs a SPI transfer which then116triggers another interrupt event.)117maxItems: 1118119patternProperties:120"^channel@[0-9a-f]+$":121type: object122$ref: adc.yaml123unevaluatedProperties: false124125properties:126reg:127description: The channel index.128minimum: 0129maximum: 271130131diff-channels:132description:133Both inputs can be connected to pins AIN1 to AIN16 by choosing the134appropriate value from 1 to 16.135items:136minimum: 1137maximum: 16138139single-channel:140description:141Positive input can be connected to pins AIN1 to AIN16 by choosing the142appropriate value from 1 to 16. Negative input is connected to AINCOM.143minimum: 1144maximum: 16145146oneOf:147- required:148- reg149- diff-channels150- required:151- reg152- single-channel153154required:155- compatible156- reg157- interrupts158- dvdd-supply159- avdd-supply160- vref-supply161- spi-cpol162- spi-cpha163164allOf:165- $ref: /schemas/spi/spi-peripheral-props.yaml#166- if:167properties:168compatible:169enum:170- adi,ad7190171- adi,ad7192172- adi,ad7193173- adi,ad7195174then:175patternProperties:176"^channel@[0-9a-f]+$": false177- if:178anyOf:179- required:180- clocks181- required:182- clock-names183then:184properties:185"#clock-cells": false186required:187- clocks188- clock-names189190unevaluatedProperties: false191192examples:193- |194#include <dt-bindings/gpio/gpio.h>195spi {196#address-cells = <1>;197#size-cells = <0>;198199adc@0 {200compatible = "adi,ad7192";201reg = <0>;202spi-max-frequency = <1000000>;203spi-cpol;204spi-cpha;205clocks = <&ad7192_mclk>;206clock-names = "mclk";207interrupts = <25 0x2>;208interrupt-parent = <&gpio>;209rdy-gpios = <&gpio 25 GPIO_ACTIVE_LOW>;210aincom-supply = <&aincom>;211dvdd-supply = <&dvdd>;212avdd-supply = <&avdd>;213vref-supply = <&vref>;214215adi,refin2-pins-enable;216adi,rejection-60-Hz-enable;217adi,buffer-enable;218adi,burnout-currents-enable;219};220};221- |222#include <dt-bindings/gpio/gpio.h>223spi {224#address-cells = <1>;225#size-cells = <0>;226227adc@0 {228compatible = "adi,ad7194";229reg = <0>;230231#address-cells = <1>;232#size-cells = <0>;233234spi-max-frequency = <1000000>;235spi-cpol;236spi-cpha;237#clock-cells = <0>;238interrupts = <25 0x2>;239interrupt-parent = <&gpio>;240rdy-gpios = <&gpio 25 GPIO_ACTIVE_LOW>;241aincom-supply = <&aincom>;242dvdd-supply = <&dvdd>;243avdd-supply = <&avdd>;244vref-supply = <&vref>;245246channel@0 {247reg = <0>;248diff-channels = <1 6>;249};250251channel@1 {252reg = <1>;253single-channel = <1>;254};255};256};257258259