Path: blob/master/Documentation/devicetree/bindings/iio/adc/adi,ad7768-1.yaml
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# SPDX-License-Identifier: GPL-2.01%YAML 1.22---3$id: http://devicetree.org/schemas/iio/adc/adi,ad7768-1.yaml#4$schema: http://devicetree.org/meta-schemas/core.yaml#56title: Analog Devices AD7768-1 ADC family78maintainers:9- Michael Hennerich <michael.hennerich@analog.com>1011description: |12Analog Devices AD7768-1 24-Bit Single Channel Low Power sigma-delta ADC family1314https://www.analog.com/media/en/technical-documentation/data-sheets/ad7768-1.pdf15https://www.analog.com/media/en/technical-documentation/data-sheets/adaq7767-1.pdf16https://www.analog.com/media/en/technical-documentation/data-sheets/adaq7768-1.pdf17https://www.analog.com/media/en/technical-documentation/data-sheets/adaq7769-1.pdf1819properties:20compatible:21enum:22- adi,ad7768-123- adi,adaq7767-124- adi,adaq7768-125- adi,adaq7769-12627reg:28maxItems: 12930clocks:31maxItems: 13233clock-names:34const: mclk3536trigger-sources:37$ref: /schemas/types.yaml#/definitions/phandle-array38minItems: 139maxItems: 240description: |41A list of phandles referencing trigger source providers. Each entry42represents a trigger source for the ADC:4344- First entry specifies the device responsible for driving the45synchronization (SYNC_IN) pin, as an alternative to adi,sync-in-gpios.46This can be a `gpio-trigger` or another `ad7768-1` device. If the47device's own SYNC_OUT pin is internally connected to its SYNC_IN pin,48reference the device itself or omit this property.49- Second entry optionally defines a GPIO3 pin used as a START signal trigger.5051Use the accompanying trigger source cell to identify the type of each entry.5253interrupts:54description:55DRDY (Data Ready) pin, which signals conversion results are available.56maxItems: 15758'#address-cells':59const: 16061'#size-cells':62const: 06364vref-supply:65description:66ADC reference voltage supply6768adi,aaf-gain-bp:69description: |70Specifies the gain applied by the Analog Anti-Aliasing Filter (AAF)71to the ADC input in basis points (one hundredth of a percent).72The hardware gain is determined by which input pin(s) the signal goes73through into the AAF. The possible connections are:74* For the ADAQ7767-1: Input connected to IN1±, IN2± or IN3±.75* For the ADAQ7769-1: OUT_PGA pin connected to IN1_AAF+, IN2_AAF+,76or IN3_AAF+.77enum: [1430, 3640, 10000]78default: 100007980pga-gpios:81description:82GAIN 0, GAIN1 and GAIN2 pins for gain selection. For devices that have83PGA configuration input pins, pga-gpios must be defined.84minItems: 385maxItems: 38687adi,sync-in-gpios:88maxItems: 189description:90Enables synchronization of multiple devices that require simultaneous91sampling. A pulse is always required if the configuration is changed92in any way, for example if the filter decimation rate changes.93As the line is active low, it should be marked GPIO_ACTIVE_LOW.9495regulators:96type: object97description:98list of regulators provided by this controller.99100properties:101vcm-output:102$ref: /schemas/regulator/regulator.yaml#103type: object104unevaluatedProperties: false105106additionalProperties: false107108reset-gpios:109maxItems: 1110111spi-cpol: true112113spi-cpha: true114115"#io-channel-cells":116const: 1117118"#trigger-source-cells":119description: |120Cell indicates the trigger output signal: 0 = SYNC_OUT, 1 = GPIO3,1212 = DRDY.122123For better readability, macros for these values are available in124dt-bindings/iio/adc/adi,ad7768-1.h.125const: 1126127gpio-controller: true128129"#gpio-cells":130const: 2131description: |132The first cell is for the GPIO number: 0 to 3.133The second cell takes standard GPIO flags.134135required:136- compatible137- reg138- clocks139- clock-names140- vref-supply141- spi-cpol142- spi-cpha143144dependencies:145adi,sync-in-gpios:146not:147required:148- trigger-sources149trigger-sources:150not:151required:152- adi,sync-in-gpios153154patternProperties:155"^channel@([0-9]|1[0-5])$":156type: object157description: |158Represents the external channels which are connected to the device.159160properties:161reg:162maxItems: 1163description: |164The channel number.165166label:167description: |168Unique name to identify which channel this is.169required:170- reg171additionalProperties: false172173allOf:174- $ref: /schemas/spi/spi-peripheral-props.yaml#175176# AAF Gain property only applies to ADAQ7767-1 and ADAQ7769-1 devices177- if:178properties:179compatible:180contains:181enum:182- adi,adaq7767-1183- adi,adaq7769-1184then:185required:186- adi,aaf-gain-bp187else:188properties:189adi,aaf-gain-bp: false190191- if:192properties:193compatible:194contains:195enum:196- adi,adaq7768-1197- adi,adaq7769-1198then:199required:200- pga-gpios201else:202properties:203pga-gpios: false204205unevaluatedProperties: false206207examples:208- |209#include <dt-bindings/interrupt-controller/irq.h>210#include <dt-bindings/gpio/gpio.h>211spi {212#address-cells = <1>;213#size-cells = <0>;214215adc@0 {216compatible = "adi,ad7768-1";217reg = <0>;218spi-max-frequency = <2000000>;219spi-cpol;220spi-cpha;221gpio-controller;222#gpio-cells = <2>;223vref-supply = <&adc_vref>;224interrupts = <25 IRQ_TYPE_EDGE_RISING>;225interrupt-parent = <&gpio>;226adi,sync-in-gpios = <&gpio 22 GPIO_ACTIVE_LOW>;227reset-gpios = <&gpio 27 GPIO_ACTIVE_LOW>;228clocks = <&ad7768_mclk>;229clock-names = "mclk";230231#address-cells = <1>;232#size-cells = <0>;233234channel@0 {235reg = <0>;236label = "channel_0";237};238239regulators {240vcm_reg: vcm-output {241regulator-name = "ad7768-1-vcm";242};243};244};245};246...247248249