Path: blob/master/Documentation/devicetree/bindings/iio/frequency/adf4371.yaml
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# SPDX-License-Identifier: GPL-2.01%YAML 1.22---3$id: http://devicetree.org/schemas/iio/frequency/adf4371.yaml#4$schema: http://devicetree.org/meta-schemas/core.yaml#56title: Analog Devices ADF4371/ADF4372 Wideband Synthesizers78maintainers:9- Popa Stefan <stefan.popa@analog.com>1011description: |12Analog Devices ADF4371/ADF4372 SPI Wideband Synthesizers13https://www.analog.com/media/en/technical-documentation/data-sheets/adf4371.pdf14https://www.analog.com/media/en/technical-documentation/data-sheets/adf4372.pdf1516properties:17compatible:18enum:19- adi,adf437120- adi,adf43722122reg:23maxItems: 12425clocks:26description:27Definition of the external clock (see clock/clock-bindings.txt)28maxItems: 12930clock-names:31description:32Must be "clkin" if the input reference is single ended or "clkin-diff"33if the input reference is differential.34enum: [clkin, clkin-diff]3536adi,mute-till-lock-en:37type: boolean38description:39If this property is present, then the supply current to RF8P and RF8N40output stage will shut down until the ADF4371/ADF4372 achieves lock as41measured by the digital lock detect circuitry.4243required:44- compatible45- reg46- clocks47- clock-names4849allOf:50- $ref: /schemas/spi/spi-peripheral-props.yaml#5152unevaluatedProperties: false5354examples:55- |56spi {57#address-cells = <1>;58#size-cells = <0>;5960frequency@0 {61compatible = "adi,adf4371";62reg = <0>;63spi-max-frequency = <1000000>;64clocks = <&adf4371_clkin>;65clock-names = "clkin";66};67};68...697071