Path: blob/master/Documentation/devicetree/bindings/iio/frequency/adi,adf4350.yaml
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)1%YAML 1.22---3$id: http://devicetree.org/schemas/iio/frequency/adi,adf4350.yaml#4$schema: http://devicetree.org/meta-schemas/core.yaml#56title: Analog Devices ADF4350/ADF4351 wideband synthesizer78maintainers:9- Michael Hennerich <michael.hennerich@analog.com>1011properties:12compatible:13enum:14- adi,adf435015- adi,adf43511617reg:18maxItems: 11920spi-max-frequency:21maximum: 200000002223clocks:24maxItems: 125description: Clock to provide CLKIN reference clock signal.2627clock-names:28const: clkin2930'#clock-cells':31const: 03233clock-output-names:34maxItems: 13536gpios:37maxItems: 138description: Lock detect GPIO.3940adi,channel-spacing:41$ref: /schemas/types.yaml#/definitions/uint3242description:43Channel spacing in Hz (influences MODULUS).4445adi,power-up-frequency:46$ref: /schemas/types.yaml#/definitions/uint3247description:48If set the PLL tunes to this frequency (in Hz) on driver probe.4950adi,reference-div-factor:51$ref: /schemas/types.yaml#/definitions/uint3252description:53If set the driver skips dynamic calculation and uses this default54value instead.5556adi,reference-doubler-enable:57$ref: /schemas/types.yaml#/definitions/flag58description: Enables reference doubler.5960adi,reference-div2-enable:61$ref: /schemas/types.yaml#/definitions/flag62description: Enables reference divider.6364adi,phase-detector-polarity-positive-enable:65$ref: /schemas/types.yaml#/definitions/flag66description: Enables positive phase detector polarity. Default negative.6768adi,lock-detect-precision-6ns-enable:69$ref: /schemas/types.yaml#/definitions/flag70description: Enables 6ns lock detect precision. Default = 10ns.7172adi,lock-detect-function-integer-n-enable:73$ref: /schemas/types.yaml#/definitions/flag74description:75Enables lock detect for integer-N mode. Default = factional-N mode.7677adi,charge-pump-current:78$ref: /schemas/types.yaml#/definitions/uint3279description: Charge pump current in mA. Default = 2500mA.8081adi,muxout-select:82$ref: /schemas/types.yaml#/definitions/uint3283minimum: 084maximum: 685description: |86On chip multiplexer output selection.87Valid values for the multiplexer output are:880: Three-State Output (default)891: DVDD902: DGND913: R-Counter output924: N-Divider output935: Analog lock detect946: Digital lock detect9596adi,low-spur-mode-enable:97$ref: /schemas/types.yaml#/definitions/flag98description: Enables low spur mode. Default = Low noise mode.99100adi,cycle-slip-reduction-enable:101$ref: /schemas/types.yaml#/definitions/flag102description: Enables cycle slip reduction.103104adi,charge-cancellation-enable:105$ref: /schemas/types.yaml#/definitions/flag106description:107Enabled charge pump charge cancellation for integer-N modes.108109adi,anti-backlash-3ns-enable:110$ref: /schemas/types.yaml#/definitions/flag111description:112Enables 3ns antibacklash pulse width for integer-N modes.113114adi,band-select-clock-mode-high-enable:115$ref: /schemas/types.yaml#/definitions/flag116description: Enables faster band selection logic.117118adi,12bit-clk-divider:119$ref: /schemas/types.yaml#/definitions/uint32120description:121Clock divider value used when adi,12bit-clkdiv-mode != 0122123adi,clk-divider-mode:124$ref: /schemas/types.yaml#/definitions/uint32125enum: [0, 1, 2]126description: |127Valid values for the clkdiv mode are:1280: Clock divider off (default)1291: Fast lock enable1302: Phase resync enable131132adi,aux-output-enable:133$ref: /schemas/types.yaml#/definitions/flag134description: Enables auxiliary RF output.135136adi,aux-output-fundamental-enable:137$ref: /schemas/types.yaml#/definitions/flag138description: |139Selects fundamental VCO output on the auxiliary RF output.140Default = Output of RF dividers.141142adi,mute-till-lock-enable:143$ref: /schemas/types.yaml#/definitions/flag144description: Enables Mute-Till-Lock-Detect function.145146adi,output-power:147$ref: /schemas/types.yaml#/definitions/uint32148enum: [0, 1, 2, 3]149description: |150Output power selection.151Valid values for the power mode are:1520: -4dBm (default)1531: -1dBm1542: +2dBm1553: +5dBm156157adi,aux-output-power:158$ref: /schemas/types.yaml#/definitions/uint32159enum: [0, 1, 2, 3]160description: |161Auxiliary output power selection.162Valid values for the power mode are:1630: -4dBm (default)1641: -1dBm1652: +2dBm1663: +5dBm167168required:169- compatible170- reg171- clocks172173allOf:174- $ref: /schemas/spi/spi-peripheral-props.yaml#175176unevaluatedProperties: false177178examples:179- |180spi {181#address-cells = <1>;182#size-cells = <0>;183184pll@4 {185compatible = "adi,adf4351";186reg = <4>;187spi-max-frequency = <10000000>;188clocks = <&clk0_ad9523 9>;189clock-names = "clkin";190adi,channel-spacing = <10000>;191adi,power-up-frequency = <2400000000>;192adi,phase-detector-polarity-positive-enable;193adi,charge-pump-current = <2500>;194adi,output-power = <3>;195adi,mute-till-lock-enable;196};197};198...199200201