Path: blob/master/arch/arm/include/debug/renesas-scif.S
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/* SPDX-License-Identifier: GPL-2.0 */1/*2* Renesas SCIF(A) debugging macro include header3*4* Based on r8a7790.S5*6* Copyright (C) 2012-2013 Renesas Electronics Corporation7* Copyright (C) 1994-1999 Russell King8*/910#define SCIF_PHYS CONFIG_DEBUG_UART_PHYS11#define SCIF_VIRT ((SCIF_PHYS & 0x00ffffff) | 0xfd000000)1213#if defined(CONFIG_DEBUG_R7S9210_SCIF2) || defined(CONFIG_DEBUG_R7S9210_SCIF4)14/* RZ/A2 SCIFA */15#define FTDR 0x0616#define FSR 0x0817#elif CONFIG_DEBUG_UART_PHYS < 0xe6e0000018/* SCIFA */19#define FTDR 0x2020#define FSR 0x1421#else22/* SCIF */23#define FTDR 0x0c24#define FSR 0x1025#endif2627#define TDFE (1 << 5)28#define TEND (1 << 6)2930.macro addruart, rp, rv, tmp31ldr \rp, =SCIF_PHYS32ldr \rv, =SCIF_VIRT33.endm3435.macro waituartcts,rd,rx36.endm3738.macro waituarttxrdy, rd, rx391001: ldrh \rd, [\rx, #FSR]40tst \rd, #TDFE41beq 1001b42.endm4344.macro senduart, rd, rx45strb \rd, [\rx, #FTDR]46ldrh \rd, [\rx, #FSR]47bic \rd, \rd, #TEND48strh \rd, [\rx, #FSR]49.endm5051.macro busyuart, rd, rx521001: ldrh \rd, [\rx, #FSR]53tst \rd, #TEND54beq 1001b55.endm565758