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torvalds
GitHub Repository: torvalds/linux
 Path: blob/master/arch/arm/mach-mvebu/pmsu_ll.S
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/* SPDX-License-Identifier: GPL-2.0-only */

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/*

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 * Copyright (C) 2014 Marvell

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 *

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 * Thomas Petazzoni <[email protected]>

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 * Gregory Clement <[email protected]>

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 */

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#include <linux/linkage.h>

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#include <asm/assembler.h>

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ENTRY(armada_38x_scu_power_up)

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	mrc     p15, 4, r1, c15, c0	@ get SCU base address

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	orr	r1, r1, #0x8		@ SCU CPU Power Status Register

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	mrc	p15, 0, r0, cr0, cr0, 5	@ get the CPU ID

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	and	r0, r0, #15

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	add	r1, r1, r0

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	mov	r0, #0x0

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	strb	r0, [r1]		@ switch SCU power state to Normal mode

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	ret	lr

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ENDPROC(armada_38x_scu_power_up)

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/*

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 * This is the entry point through which CPUs exiting cpuidle deep

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 * idle state are going.

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 */

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ENTRY(armada_370_xp_cpu_resume)

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ARM_BE8(setend	be )			@ go BE8 if entered LE

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	/*

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	 * Disable the MMU that might have been enabled in BootROM if

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	 * this code is used in the resume path of a suspend/resume

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	 * cycle.

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	 */

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	mrc	p15, 0, r1, c1, c0, 0

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	bic	r1, #1

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	mcr	p15, 0, r1, c1, c0, 0

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	bl	ll_add_cpu_to_smp_group

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	bl	ll_enable_coherency

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	b	cpu_resume

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ENDPROC(armada_370_xp_cpu_resume)

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ENTRY(armada_38x_cpu_resume)

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	/* do we need it for Armada 38x*/

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ARM_BE8(setend	be )			@ go BE8 if entered LE

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	bl	v7_invalidate_l1

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	bl	armada_38x_scu_power_up

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	b	cpu_resume

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ENDPROC(armada_38x_cpu_resume)

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.global mvebu_boot_wa_start

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.global mvebu_boot_wa_end

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/* The following code will be executed from SRAM */

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ENTRY(mvebu_boot_wa_start)

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ARM_BE8(setend	be)

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	adr	r0, 1f

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	ldr	r0, [r0]		@ load the address of the

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					@ resume register

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	ldr	r0, [r0]		@ load the value in the

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					@ resume register

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ARM_BE8(rev	r0, r0)			@ the value is stored LE

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	mov	pc, r0			@ jump to this value

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/*

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 * the last word of this piece of code will be filled by the physical

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 * address of the boot address register just after being copied in SRAM

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 */

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1:

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	.long   .

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mvebu_boot_wa_end:

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ENDPROC(mvebu_boot_wa_end)

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