/* SPDX-License-Identifier: GPL-2.0-only */1/*2* OMAP2+ Clock Management prototypes3*4* Copyright (C) 2007-2009, 2012 Texas Instruments, Inc.5* Copyright (C) 2007-2009 Nokia Corporation6*7* Written by Paul Walmsley8*/9#ifndef __ARCH_ASM_MACH_OMAP2_CM_H10#define __ARCH_ASM_MACH_OMAP2_CM_H1112/*13* MAX_MODULE_READY_TIME: max duration in microseconds to wait for the14* PRCM to request that a module exit the inactive state in the case of15* OMAP2 & 3.16* In the case of OMAP4 this is the max duration in microseconds for the17* module to reach the functionnal state from an inactive state.18*/19#define MAX_MODULE_READY_TIME 20002021# ifndef __ASSEMBLER__22#include <linux/clk/ti.h>2324#include "prcm-common.h"2526extern struct omap_domain_base cm_base;27extern struct omap_domain_base cm2_base;28# endif2930/*31* MAX_MODULE_DISABLE_TIME: max duration in microseconds to wait for32* the PRCM to request that a module enter the inactive state in the33* case of OMAP2 & 3. In the case of OMAP4 this is the max duration34* in microseconds for the module to reach the inactive state from35* a functional state.36* XXX FSUSB on OMAP4430 takes ~4ms to idle after reset during37* kernel init.38*/39#define MAX_MODULE_DISABLE_TIME 50004041# ifndef __ASSEMBLER__4243/**44* struct cm_ll_data - fn ptrs to per-SoC CM function implementations45* @split_idlest_reg: ptr to the SoC CM-specific split_idlest_reg impl46* @wait_module_ready: ptr to the SoC CM-specific wait_module_ready impl47* @wait_module_idle: ptr to the SoC CM-specific wait_module_idle impl48* @module_enable: ptr to the SoC CM-specific module_enable impl49* @module_disable: ptr to the SoC CM-specific module_disable impl50* @xlate_clkctrl: ptr to the SoC CM-specific clkctrl xlate addr impl51*/52struct cm_ll_data {53int (*split_idlest_reg)(struct clk_omap_reg *idlest_reg, s16 *prcm_inst,54u8 *idlest_reg_id);55int (*wait_module_ready)(u8 part, s16 prcm_mod, u16 idlest_reg,56u8 idlest_shift);57int (*wait_module_idle)(u8 part, s16 prcm_mod, u16 idlest_reg,58u8 idlest_shift);59void (*module_enable)(u8 mode, u8 part, u16 inst, u16 clkctrl_offs);60void (*module_disable)(u8 part, u16 inst, u16 clkctrl_offs);61u32 (*xlate_clkctrl)(u8 part, u16 inst, u16 clkctrl_offs);62};6364extern int cm_split_idlest_reg(struct clk_omap_reg *idlest_reg, s16 *prcm_inst,65u8 *idlest_reg_id);66int omap_cm_wait_module_ready(u8 part, s16 prcm_mod, u16 idlest_reg,67u8 idlest_shift);68int omap_cm_wait_module_idle(u8 part, s16 prcm_mod, u16 idlest_reg,69u8 idlest_shift);70int omap_cm_module_enable(u8 mode, u8 part, u16 inst, u16 clkctrl_offs);71int omap_cm_module_disable(u8 part, u16 inst, u16 clkctrl_offs);72u32 omap_cm_xlate_clkctrl(u8 part, u16 inst, u16 clkctrl_offs);73extern int cm_register(const struct cm_ll_data *cld);74extern int cm_unregister(const struct cm_ll_data *cld);75int omap_cm_init(void);76int omap2_cm_base_init(void);7778# endif7980#endif818283