/* SPDX-License-Identifier: GPL-2.0-only */1/*2* OMAP54xx CM1 instance offset macros3*4* Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com5*6* Paul Walmsley ([email protected])7* Rajendra Nayak ([email protected])8* Benoit Cousson ([email protected])9*10* This file is automatically generated from the OMAP hardware databases.11* We respectfully ask that any modifications to this file be coordinated12* with the public [email protected] mailing list and the13* authors above to ensure that the autogeneration scripts are kept14* up-to-date with the file contents.15*/1617#ifndef __ARCH_ARM_MACH_OMAP2_CM1_54XX_H18#define __ARCH_ARM_MACH_OMAP2_CM1_54XX_H1920/* CM1 base address */21#define OMAP54XX_CM_CORE_AON_BASE 0x4a0040002223#define OMAP54XX_CM_CORE_AON_REGADDR(inst, reg) \24OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE + (inst) + (reg))2526/* CM_CORE_AON instances */27#define OMAP54XX_CM_CORE_AON_OCP_SOCKET_INST 0x000028#define OMAP54XX_CM_CORE_AON_CKGEN_INST 0x010029#define OMAP54XX_CM_CORE_AON_MPU_INST 0x030030#define OMAP54XX_CM_CORE_AON_DSP_INST 0x040031#define OMAP54XX_CM_CORE_AON_ABE_INST 0x05003233/* CM_CORE_AON clockdomain register offsets (from instance start) */34#define OMAP54XX_CM_CORE_AON_MPU_MPU_CDOFFS 0x000035#define OMAP54XX_CM_CORE_AON_DSP_DSP_CDOFFS 0x000036#define OMAP54XX_CM_CORE_AON_ABE_ABE_CDOFFS 0x00003738#endif394041