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torvalds
GitHub Repository: torvalds/linux
 Path: blob/master/arch/arm/mach-omap2/cm1_7xx.h
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/* SPDX-License-Identifier: GPL-2.0-only */

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/*

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 * DRA7xx CM1 instance offset macros

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 *

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 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com

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 *

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 * Generated by code originally written by:

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 * Paul Walmsley ([email protected])

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 * Rajendra Nayak ([email protected])

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 * Benoit Cousson ([email protected])

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 *

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 * This file is automatically generated from the OMAP hardware databases.

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 * We respectfully ask that any modifications to this file be coordinated

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 * with the public [email protected] mailing list and the

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 * authors above to ensure that the autogeneration scripts are kept

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 * up-to-date with the file contents.

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 */

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#ifndef __ARCH_ARM_MACH_OMAP2_CM1_7XX_H

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#define __ARCH_ARM_MACH_OMAP2_CM1_7XX_H

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/* CM1 base address */

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#define DRA7XX_CM_CORE_AON_BASE		0x4a005000

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#define DRA7XX_CM_CORE_AON_REGADDR(inst, reg)				\

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	OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_AON_BASE + (inst) + (reg))

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/* CM_CORE_AON instances */

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#define DRA7XX_CM_CORE_AON_OCP_SOCKET_INST	0x0000

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#define DRA7XX_CM_CORE_AON_CKGEN_INST		0x0100

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#define DRA7XX_CM_CORE_AON_MPU_INST		0x0300

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#define DRA7XX_CM_CORE_AON_DSP1_INST		0x0400

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#define DRA7XX_CM_CORE_AON_IPU_INST		0x0500

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#define DRA7XX_CM_CORE_AON_DSP2_INST		0x0600

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#define DRA7XX_CM_CORE_AON_EVE1_INST		0x0640

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#define DRA7XX_CM_CORE_AON_EVE2_INST		0x0680

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#define DRA7XX_CM_CORE_AON_EVE3_INST		0x06c0

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#define DRA7XX_CM_CORE_AON_EVE4_INST		0x0700

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#define DRA7XX_CM_CORE_AON_RTC_INST		0x0740

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#define DRA7XX_CM_CORE_AON_VPE_INST		0x0760

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/* CM_CORE_AON clockdomain register offsets (from instance start) */

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#define DRA7XX_CM_CORE_AON_MPU_MPU_CDOFFS	0x0000

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#define DRA7XX_CM_CORE_AON_DSP1_DSP1_CDOFFS	0x0000

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#define DRA7XX_CM_CORE_AON_IPU_IPU1_CDOFFS	0x0000

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#define DRA7XX_CM_CORE_AON_IPU_IPU_CDOFFS	0x0040

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#define DRA7XX_CM_CORE_AON_DSP2_DSP2_CDOFFS	0x0000

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#define DRA7XX_CM_CORE_AON_EVE1_EVE1_CDOFFS	0x0000

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#define DRA7XX_CM_CORE_AON_EVE2_EVE2_CDOFFS	0x0000

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#define DRA7XX_CM_CORE_AON_EVE3_EVE3_CDOFFS	0x0000

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#define DRA7XX_CM_CORE_AON_EVE4_EVE4_CDOFFS	0x0000

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#define DRA7XX_CM_CORE_AON_RTC_RTC_CDOFFS	0x0000

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#define DRA7XX_CM_CORE_AON_VPE_VPE_CDOFFS	0x0000

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#endif

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