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torvalds
GitHub Repository: torvalds/linux
 Path: blob/master/arch/arm/mach-omap2/cm2_7xx.h
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/* SPDX-License-Identifier: GPL-2.0-only */

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/*

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 * DRA7xx CM2 instance offset macros

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 *

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 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com

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 *

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 * Generated by code originally written by:

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 * Paul Walmsley ([email protected])

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 * Rajendra Nayak ([email protected])

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 * Benoit Cousson ([email protected])

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 *

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 * This file is automatically generated from the OMAP hardware databases.

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 * We respectfully ask that any modifications to this file be coordinated

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 * with the public [email protected] mailing list and the

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 * authors above to ensure that the autogeneration scripts are kept

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 * up-to-date with the file contents.

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 */

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#ifndef __ARCH_ARM_MACH_OMAP2_CM2_7XX_H

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#define __ARCH_ARM_MACH_OMAP2_CM2_7XX_H

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/* CM2 base address */

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#define DRA7XX_CM_CORE_BASE		0x4a008000

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#define DRA7XX_CM_CORE_REGADDR(inst, reg)				\

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	OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_BASE + (inst) + (reg))

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/* CM_CORE instances */

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#define DRA7XX_CM_CORE_OCP_SOCKET_INST	0x0000

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#define DRA7XX_CM_CORE_CKGEN_INST	0x0104

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#define DRA7XX_CM_CORE_COREAON_INST	0x0600

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#define DRA7XX_CM_CORE_CORE_INST	0x0700

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#define DRA7XX_CM_CORE_IVA_INST		0x0f00

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#define DRA7XX_CM_CORE_CAM_INST		0x1000

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#define DRA7XX_CM_CORE_DSS_INST		0x1100

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#define DRA7XX_CM_CORE_GPU_INST		0x1200

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#define DRA7XX_CM_CORE_L3INIT_INST	0x1300

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#define DRA7XX_CM_CORE_CUSTEFUSE_INST	0x1600

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#define DRA7XX_CM_CORE_L4PER_INST	0x1700

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/* CM_CORE clockdomain register offsets (from instance start) */

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#define DRA7XX_CM_CORE_COREAON_COREAON_CDOFFS		0x0000

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#define DRA7XX_CM_CORE_CORE_L3MAIN1_CDOFFS		0x0000

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#define DRA7XX_CM_CORE_CORE_IPU2_CDOFFS			0x0200

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#define DRA7XX_CM_CORE_CORE_DMA_CDOFFS			0x0300

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#define DRA7XX_CM_CORE_CORE_EMIF_CDOFFS			0x0400

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#define DRA7XX_CM_CORE_CORE_ATL_CDOFFS			0x0520

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#define DRA7XX_CM_CORE_CORE_L4CFG_CDOFFS		0x0600

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#define DRA7XX_CM_CORE_CORE_L3INSTR_CDOFFS		0x0700

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#define DRA7XX_CM_CORE_IVA_IVA_CDOFFS			0x0000

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#define DRA7XX_CM_CORE_CAM_CAM_CDOFFS			0x0000

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#define DRA7XX_CM_CORE_DSS_DSS_CDOFFS			0x0000

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#define DRA7XX_CM_CORE_GPU_GPU_CDOFFS			0x0000

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#define DRA7XX_CM_CORE_L3INIT_L3INIT_CDOFFS		0x0000

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#define DRA7XX_CM_CORE_L3INIT_PCIE_CDOFFS		0x00a0

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#define DRA7XX_CM_CORE_L3INIT_GMAC_CDOFFS		0x00c0

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#define DRA7XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS	0x0000

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#define DRA7XX_CM_CORE_L4PER_L4PER_CDOFFS		0x0000

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#define DRA7XX_CM_CORE_L4PER_L4SEC_CDOFFS		0x0180

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#define DRA7XX_CM_CORE_L4PER_L4PER2_CDOFFS		0x01fc

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#define DRA7XX_CM_CORE_L4PER_L4PER3_CDOFFS		0x0210

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#endif

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