Path: blob/master/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2020 Yangtao Li <[email protected]> */ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/sun50i-a100-ccu.h> #include <dt-bindings/clock/sun50i-a100-r-ccu.h> #include <dt-bindings/reset/sun50i-a100-ccu.h> #include <dt-bindings/reset/sun50i-a100-r-ccu.h> / { interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <0x0>; enable-method = "psci"; clocks = <&ccu CLK_CPUX>; }; cpu1: cpu@1 { compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <0x1>; enable-method = "psci"; clocks = <&ccu CLK_CPUX>; }; cpu2: cpu@2 { compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <0x2>; enable-method = "psci"; clocks = <&ccu CLK_CPUX>; }; cpu3: cpu@3 { compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <0x3>; enable-method = "psci"; clocks = <&ccu CLK_CPUX>; }; }; pmu { compatible = "arm,cortex-a53-pmu"; interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; }; psci { compatible = "arm,psci-1.0"; method = "smc"; }; dcxo24M: dcxo24M-clk { compatible = "fixed-clock"; clock-frequency = <24000000>; clock-output-names = "dcxo24M"; #clock-cells = <0>; }; iosc: internal-osc-clk { compatible = "fixed-clock"; clock-frequency = <16000000>; clock-accuracy = <300000000>; clock-output-names = "iosc"; #clock-cells = <0>; }; osc32k: osc32k-clk { compatible = "fixed-clock"; clock-frequency = <32768>; clock-output-names = "osc32k"; #clock-cells = <0>; }; timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; soc { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0 0x3fffffff>; syscon: syscon@3000000 { compatible = "allwinner,sun50i-a100-system-control", "allwinner,sun50i-a64-system-control"; reg = <0x03000000 0x1000>; #address-cells = <1>; #size-cells = <1>; ranges; sram_a1: sram@20000 { compatible = "mmio-sram"; reg = <0x00020000 0x4000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x00020000 0x4000>; }; sram_c: sram@24000 { compatible = "mmio-sram"; reg = <0x024000 0x21000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x024000 0x21000>; }; sram_a2: sram@100000 { compatible = "mmio-sram"; reg = <0x0100000 0x14000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x0100000 0x14000>; }; }; ccu: clock@3001000 { compatible = "allwinner,sun50i-a100-ccu"; reg = <0x03001000 0x1000>; clocks = <&dcxo24M>, <&osc32k>, <&iosc>; clock-names = "hosc", "losc", "iosc"; #clock-cells = <1>; #reset-cells = <1>; }; dma: dma-controller@3002000 { compatible = "allwinner,sun50i-a100-dma"; reg = <0x03002000 0x1000>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>; clock-names = "bus", "mbus"; resets = <&ccu RST_BUS_DMA>; dma-channels = <8>; dma-requests = <52>; #dma-cells = <1>; }; gic: interrupt-controller@3021000 { compatible = "arm,gic-400"; reg = <0x03021000 0x1000>, <0x03022000 0x2000>, <0x03024000 0x2000>, <0x03026000 0x2000>; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; interrupt-controller; #interrupt-cells = <3>; }; efuse@3006000 { compatible = "allwinner,sun50i-a100-sid", "allwinner,sun50i-a64-sid"; reg = <0x03006000 0x1000>; #address-cells = <1>; #size-cells = <1>; ths_calibration: calib@14 { reg = <0x14 8>; }; cpu_speed_grade: cpu-speed-grade@1c { reg = <0x1c 0x2>; }; }; watchdog@30090a0 { compatible = "allwinner,sun50i-a100-wdt", "allwinner,sun6i-a31-wdt"; reg = <0x030090a0 0x20>; interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; clocks = <&dcxo24M>; }; pio: pinctrl@300b000 { compatible = "allwinner,sun50i-a100-pinctrl"; reg = <0x0300b000 0x400>; interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_APB1>, <&dcxo24M>, <&osc32k>; clock-names = "apb", "hosc", "losc"; gpio-controller; #gpio-cells = <3>; interrupt-controller; #interrupt-cells = <3>; mmc0_pins: mmc0-pins { pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; function = "mmc0"; drive-strength = <30>; bias-pull-up; }; /omit-if-no-ref/ mmc1_pins: mmc1-pins { pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5"; function = "mmc1"; drive-strength = <30>; bias-pull-up; }; mmc2_pins: mmc2-pins { pins = "PC0", "PC1", "PC5", "PC6", "PC8", "PC9", "PC10", "PC11", "PC13", "PC14", "PC15", "PC16"; function = "mmc2"; drive-strength = <30>; bias-pull-up; }; rgmii0_pins: rgmii0-pins { pins = "PH0", "PH1", "PH2", "PH3", "PH4", "PH5", "PH6", "PH7", "PH9", "PH10", "PH14", "PH15", "PH16", "PH17", "PH18"; function = "emac0"; drive-strength = <40>; }; rmii0_pins: rmii0-pins { pins = "PH0", "PH1", "PH2", "PH3", "PH4", "PH5", "PH6", "PH7", "PH9", "PH10"; function = "emac0"; drive-strength = <40>; }; uart0_pb_pins: uart0-pb-pins { pins = "PB9", "PB10"; function = "uart0"; }; }; mmc0: mmc@4020000 { compatible = "allwinner,sun50i-a100-mmc"; reg = <0x04020000 0x1000>; clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; clock-names = "ahb", "mmc"; resets = <&ccu RST_BUS_MMC0>; reset-names = "ahb"; interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>; max-frequency = <150000000>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; mmc1: mmc@4021000 { compatible = "allwinner,sun50i-a100-mmc"; reg = <0x04021000 0x1000>; clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; clock-names = "ahb", "mmc"; resets = <&ccu RST_BUS_MMC1>; reset-names = "ahb"; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins>; max-frequency = <150000000>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; mmc2: mmc@4022000 { compatible = "allwinner,sun50i-a100-emmc"; reg = <0x04022000 0x1000>; clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; clock-names = "ahb", "mmc"; resets = <&ccu RST_BUS_MMC2>; reset-names = "ahb"; interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&mmc2_pins>; max-frequency = <150000000>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; uart0: serial@5000000 { compatible = "snps,dw-apb-uart"; reg = <0x05000000 0x400>; interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; clocks = <&ccu CLK_BUS_UART0>; resets = <&ccu RST_BUS_UART0>; status = "disabled"; }; uart1: serial@5000400 { compatible = "snps,dw-apb-uart"; reg = <0x05000400 0x400>; interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; clocks = <&ccu CLK_BUS_UART1>; resets = <&ccu RST_BUS_UART1>; status = "disabled"; }; uart2: serial@5000800 { compatible = "snps,dw-apb-uart"; reg = <0x05000800 0x400>; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; clocks = <&ccu CLK_BUS_UART2>; resets = <&ccu RST_BUS_UART2>; status = "disabled"; }; uart3: serial@5000c00 { compatible = "snps,dw-apb-uart"; reg = <0x05000c00 0x400>; interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; clocks = <&ccu CLK_BUS_UART3>; resets = <&ccu RST_BUS_UART3>; status = "disabled"; }; uart4: serial@5001000 { compatible = "snps,dw-apb-uart"; reg = <0x05001000 0x400>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; clocks = <&ccu CLK_BUS_UART4>; resets = <&ccu RST_BUS_UART4>; status = "disabled"; }; i2c0: i2c@5002000 { compatible = "allwinner,sun50i-a100-i2c", "allwinner,sun8i-v536-i2c", "allwinner,sun6i-a31-i2c"; reg = <0x05002000 0x400>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_I2C0>; resets = <&ccu RST_BUS_I2C0>; dmas = <&dma 43>, <&dma 43>; dma-names = "rx", "tx"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; i2c1: i2c@5002400 { compatible = "allwinner,sun50i-a100-i2c", "allwinner,sun8i-v536-i2c", "allwinner,sun6i-a31-i2c"; reg = <0x05002400 0x400>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_I2C1>; resets = <&ccu RST_BUS_I2C1>; dmas = <&dma 44>, <&dma 44>; dma-names = "rx", "tx"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; i2c2: i2c@5002800 { compatible = "allwinner,sun50i-a100-i2c", "allwinner,sun8i-v536-i2c", "allwinner,sun6i-a31-i2c"; reg = <0x05002800 0x400>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_I2C2>; resets = <&ccu RST_BUS_I2C2>; dmas = <&dma 45>, <&dma 45>; dma-names = "rx", "tx"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; i2c3: i2c@5002c00 { compatible = "allwinner,sun50i-a100-i2c", "allwinner,sun8i-v536-i2c", "allwinner,sun6i-a31-i2c"; reg = <0x05002c00 0x400>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_I2C3>; resets = <&ccu RST_BUS_I2C3>; dmas = <&dma 46>, <&dma 46>; dma-names = "rx", "tx"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; emac0: ethernet@5020000 { compatible = "allwinner,sun50i-a100-emac", "allwinner,sun50i-a64-emac"; reg = <0x5020000 0x10000>; interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq"; clocks = <&ccu CLK_BUS_EMAC>; clock-names = "stmmaceth"; resets = <&ccu RST_BUS_EMAC>; reset-names = "stmmaceth"; syscon = <&syscon>; status = "disabled"; mdio0: mdio { compatible = "snps,dwmac-mdio"; #address-cells = <1>; #size-cells = <0>; }; }; ths: thermal-sensor@5070400 { compatible = "allwinner,sun50i-a100-ths"; reg = <0x05070400 0x100>; interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_THS>; clock-names = "bus"; resets = <&ccu RST_BUS_THS>; nvmem-cells = <&ths_calibration>; nvmem-cell-names = "calibration"; #thermal-sensor-cells = <1>; }; usb_otg: usb@5100000 { compatible = "allwinner,sun50i-a100-musb", "allwinner,sun8i-a33-musb"; reg = <0x05100000 0x0400>; clocks = <&ccu CLK_BUS_OTG>; resets = <&ccu RST_BUS_OTG>; interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "mc"; phys = <&usbphy 0>; phy-names = "usb"; extcon = <&usbphy 0>; status = "disabled"; }; usbphy: phy@5100400 { compatible = "allwinner,sun50i-a100-usb-phy", "allwinner,sun20i-d1-usb-phy"; reg = <0x05100400 0x100>, <0x05101800 0x100>, <0x05200800 0x100>; reg-names = "phy_ctrl", "pmu0", "pmu1"; clocks = <&ccu CLK_USB_PHY0>, <&ccu CLK_USB_PHY1>; clock-names = "usb0_phy", "usb1_phy"; resets = <&ccu RST_USB_PHY0>, <&ccu RST_USB_PHY1>; reset-names = "usb0_reset", "usb1_reset"; status = "disabled"; #phy-cells = <1>; }; ehci0: usb@5101000 { compatible = "allwinner,sun50i-a100-ehci", "generic-ehci"; reg = <0x05101000 0x100>; interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_OHCI0>, <&ccu CLK_BUS_EHCI0>, <&ccu CLK_USB_OHCI0>; resets = <&ccu RST_BUS_OHCI0>, <&ccu RST_BUS_EHCI0>; phys = <&usbphy 0>; phy-names = "usb"; status = "disabled"; }; ohci0: usb@5101400 { compatible = "allwinner,sun50i-a100-ohci", "generic-ohci"; reg = <0x05101400 0x100>; interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_OHCI0>, <&ccu CLK_USB_OHCI0>; resets = <&ccu RST_BUS_OHCI0>; phys = <&usbphy 0>; phy-names = "usb"; status = "disabled"; }; ehci1: usb@5200000 { compatible = "allwinner,sun50i-a100-ehci", "generic-ehci"; reg = <0x05200000 0x100>; interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_OHCI1>, <&ccu CLK_BUS_EHCI1>, <&ccu CLK_USB_OHCI1>; resets = <&ccu RST_BUS_OHCI1>, <&ccu RST_BUS_EHCI1>; phys = <&usbphy 1>; phy-names = "usb"; status = "disabled"; }; ohci1: usb@5200400 { compatible = "allwinner,sun50i-a100-ohci", "generic-ohci"; reg = <0x05200400 0x100>; interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_OHCI1>, <&ccu CLK_USB_OHCI1>; resets = <&ccu RST_BUS_OHCI1>; phys = <&usbphy 1>; phy-names = "usb"; status = "disabled"; }; r_ccu: clock@7010000 { compatible = "allwinner,sun50i-a100-r-ccu"; reg = <0x07010000 0x300>; clocks = <&dcxo24M>, <&osc32k>, <&iosc>, <&ccu CLK_PLL_PERIPH0>; clock-names = "hosc", "losc", "iosc", "pll-periph"; #clock-cells = <1>; #reset-cells = <1>; }; r_intc: interrupt-controller@7010320 { compatible = "allwinner,sun50i-a100-nmi", "allwinner,sun9i-a80-nmi"; interrupt-controller; #interrupt-cells = <2>; reg = <0x07010320 0xc>; interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; }; r_pio: pinctrl@7022000 { compatible = "allwinner,sun50i-a100-r-pinctrl"; reg = <0x07022000 0x400>; interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; clocks = <&r_ccu CLK_R_APB1>, <&dcxo24M>, <&osc32k>; clock-names = "apb", "hosc", "losc"; gpio-controller; #gpio-cells = <3>; interrupt-controller; #interrupt-cells = <3>; r_i2c0_pins: r-i2c0-pins { pins = "PL0", "PL1"; function = "s_i2c0"; }; r_i2c1_pins: r-i2c1-pins { pins = "PL8", "PL9"; function = "s_i2c1"; }; }; r_uart: serial@7080000 { compatible = "snps,dw-apb-uart"; reg = <0x07080000 0x400>; interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; clocks = <&r_ccu CLK_R_APB2_UART>; resets = <&r_ccu RST_R_APB2_UART>; status = "disabled"; }; r_i2c0: i2c@7081400 { compatible = "allwinner,sun50i-a100-i2c", "allwinner,sun8i-v536-i2c", "allwinner,sun6i-a31-i2c"; reg = <0x07081400 0x400>; interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; clocks = <&r_ccu CLK_R_APB2_I2C0>; resets = <&r_ccu RST_R_APB2_I2C0>; dmas = <&dma 50>, <&dma 50>; dma-names = "rx", "tx"; pinctrl-names = "default"; pinctrl-0 = <&r_i2c0_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; r_i2c1: i2c@7081800 { compatible = "allwinner,sun50i-a100-i2c", "allwinner,sun8i-v536-i2c", "allwinner,sun6i-a31-i2c"; reg = <0x07081800 0x400>; interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; clocks = <&r_ccu CLK_R_APB2_I2C1>; resets = <&r_ccu RST_R_APB2_I2C1>; dmas = <&dma 51>, <&dma 51>; dma-names = "rx", "tx"; pinctrl-names = "default"; pinctrl-0 = <&r_i2c1_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; }; thermal-zones { cpu-thermal { polling-delay-passive = <0>; polling-delay = <0>; thermal-sensors = <&ths 0>; }; ddr-thermal { polling-delay-passive = <0>; polling-delay = <0>; thermal-sensors = <&ths 2>; }; gpu-thermal { polling-delay-passive = <0>; polling-delay = <0>; thermal-sensors = <&ths 1>; }; }; };