Path: blob/master/arch/arm64/boot/dts/amlogic/amlogic-a5-reset.h
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/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */1/*2* Copyright (c) 2024 Amlogic, Inc. All rights reserved.3*/45#ifndef __DTS_AMLOGIC_A5_RESET_H6#define __DTS_AMLOGIC_A5_RESET_H78/* RESET0 */9/* 0-3 */10#define RESET_USB 411/* 5-7 */12#define RESET_USBPHY20 813/* 9 */14#define RESET_USB2DRD 1015/* 11-31 */1617/* RESET1 */18#define RESET_AUDIO 3219#define RESET_AUDIO_VAD 3320/* 34 */21#define RESET_DDR_APB 3522#define RESET_DDR 3623/* 37-40 */24#define RESET_DSPA_DEBUG 4125/* 42 */26#define RESET_DSPA 4327/* 44-46 */28#define RESET_NNA 4729#define RESET_ETHERNET 4830/* 49-63 */3132/* RESET2 */33#define RESET_ABUS_ARB 6434#define RESET_IRCTRL 6535/* 66 */36#define RESET_TS_PLL 6737/* 68-72 */38#define RESET_SPICC_0 7339#define RESET_SPICC_1 7440#define RESET_RSA 754142/* 76-79 */43#define RESET_MSR_CLK 8044#define RESET_SPIFC 8145#define RESET_SAR_ADC 8246/* 83-90 */47#define RESET_WATCHDOG 9148/* 92-95 */4950/* RESET3 */51/* 96-127 */5253/* RESET4 */54#define RESET_RTC 12855/* 129-131 */56#define RESET_PWM_AB 13257#define RESET_PWM_CD 13358#define RESET_PWM_EF 13459#define RESET_PWM_GH 13560/* 104-105 */61#define RESET_UART_A 13862#define RESET_UART_B 13963#define RESET_UART_C 14064#define RESET_UART_D 14165#define RESET_UART_E 14266/* 143*/67#define RESET_I2C_S_A 14468#define RESET_I2C_M_A 14569#define RESET_I2C_M_B 14670#define RESET_I2C_M_C 14771#define RESET_I2C_M_D 14872/* 149-151 */73#define RESET_SDEMMC_A 15274/* 153 */75#define RESET_SDEMMC_C 15476/* 155-159*/7778/* RESET5 */79/* 160-175 */80#define RESET_BRG_AO_NIC_SYS 17681#define RESET_BRG_AO_NIC_DSPA 17782#define RESET_BRG_AO_NIC_MAIN 17883#define RESET_BRG_AO_NIC_AUDIO 17984/* 180-183 */85#define RESET_BRG_AO_NIC_ALL 18486#define RESET_BRG_NIC_NNA 18587#define RESET_BRG_NIC_SDIO 18688#define RESET_BRG_NIC_EMMC 18789#define RESET_BRG_NIC_DSU 18890#define RESET_BRG_NIC_SYSCLK 18991#define RESET_BRG_NIC_MAIN 19092#define RESET_BRG_NIC_ALL 1919394#endif959697