amlogic-a5.dtsi

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2024 Amlogic, Inc. All rights reserved.
 */

#include "amlogic-a4-common.dtsi"
#include "amlogic-a5-reset.h"
#include <dt-bindings/pinctrl/amlogic,pinctrl.h>
#include <dt-bindings/power/amlogic,a5-pwrc.h>
/ {
	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x0 0x0>;
			enable-method = "psci";
		};

		cpu1: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x0 0x100>;
			enable-method = "psci";
		};

		cpu2: cpu@200 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x0 0x200>;
			enable-method = "psci";
		};

		cpu3: cpu@300 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x0 0x300>;
			enable-method = "psci";
		};
	};

	sm: secure-monitor {
		compatible = "amlogic,meson-gxbb-sm";

		pwrc: power-controller {
			compatible = "amlogic,a5-pwrc";
			#power-domain-cells = <1>;
		};
	};
};

&apb {
	reset: reset-controller@2000 {
		compatible = "amlogic,a5-reset",
			     "amlogic,meson-s4-reset";
		reg = <0x0 0x2000 0x0 0x98>;
		#reset-cells = <1>;
	};

	periphs_pinctrl: pinctrl@4000 {
		compatible = "amlogic,pinctrl-a5",
			     "amlogic,pinctrl-a4";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges = <0x0 0x0 0x0 0x4000 0x0 0x300>;

		gpioz: gpio@c0 {
			reg = <0x0 0xc0 0x0 0x40>,
			      <0x0 0x18 0x0 0x8>;
			reg-names = "gpio", "mux";
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_Z<<8) 16>;
		};

		gpiox: gpio@100 {
			reg = <0x0 0x100 0x0 0x40>,
			      <0x0 0xc   0x0 0xc>;
			reg-names = "gpio", "mux";
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_X<<8) 20>;
		};

		gpiot: gpio@140 {
			reg = <0x0 0x140 0x0 0x40>,
			      <0x0 0x2c  0x0 0x8>;
			reg-names = "gpio", "mux";
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_T<<8) 14>;
		};

		gpiod: gpio@180 {
			reg = <0x0 0x180 0x0 0x40>,
			      <0x0 0x40  0x0 0x8>;
			reg-names = "gpio", "mux";
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_D<<8) 16>;
		};

		gpioe: gpio@1c0 {
			reg = <0x0 0x1c0 0x0 0x40>,
			      <0x0 0x48  0x0 0x4>;
			reg-names = "gpio", "mux";
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_E<<8) 2>;
		};

		gpioc: gpio@200 {
			reg = <0x0 0x200 0x0 0x40>,
			      <0x0 0x24  0x0 0x8>;
			reg-names = "gpio", "mux";
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_C<<8) 11>;
		};

		gpiob: gpio@240 {
			reg = <0x0 0x240 0x0 0x40>,
			      <0x0 0x0   0x0 0x8>;
			reg-names = "gpio", "mux";
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_B<<8) 14>;
		};

		gpioh: gpio@280 {
			reg = <0x0 0x280 0x0 0x40>,
			      <0x0 0x4c  0x0 0x4>;
			reg-names = "gpio", "mux";
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_H<<8) 5>;
		};

		gpio_test_n: gpio@2c0 {
			reg = <0x0 0x2c0 0x0 0x40>,
			      <0x0 0x3c  0x0 0x4>;
			reg-names = "gpio", "mux";
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_TEST_N<<8) 1>;
		};
	};

	gpio_intc: interrupt-controller@4080 {
		compatible = "amlogic,a5-gpio-intc",
			     "amlogic,meson-gpio-intc";
		reg = <0x0 0x4080 0x0 0x20>;
		interrupt-controller;
		#interrupt-cells = <2>;
		amlogic,channel-interrupts =
			<10 11 12 13 14 15 16 17 18 19 20 21>;
	};
};