s800-0-3.dtsi

// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
 * Apple S8000/S8003 "A9" SoC
 *
 * This file contains parts common to both variants of A9
 *
 * Copyright (c) 2022, Konrad Dybcio <[email protected]>
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/apple-aic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/apple.h>

/ {
	interrupt-parent = <&aic>;
	#address-cells = <2>;
	#size-cells = <2>;

	clkref: clock-ref {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <24000000>;
		clock-output-names = "clkref";
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "apple,twister";
			reg = <0x0 0x0>;
			cpu-release-addr = <0 0>; /* To be filled in by loader */
			operating-points-v2 = <&twister_opp>;
			performance-domains = <&cpufreq>;
			enable-method = "spin-table";
			device_type = "cpu";
			next-level-cache = <&l2_cache>;
			i-cache-size = <0x10000>;
			d-cache-size = <0x10000>;
		};

		cpu1: cpu@1 {
			compatible = "apple,twister";
			reg = <0x0 0x1>;
			cpu-release-addr = <0 0>; /* To be filled in by loader */
			operating-points-v2 = <&twister_opp>;
			performance-domains = <&cpufreq>;
			enable-method = "spin-table";
			device_type = "cpu";
			next-level-cache = <&l2_cache>;
			i-cache-size = <0x10000>;
			d-cache-size = <0x10000>;
		};

		l2_cache: l2-cache {
			compatible = "cache";
			cache-level = <2>;
			cache-unified;
			cache-size = <0x300000>;
		};
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		nonposted-mmio;
		ranges;

		cpufreq: performance-controller@202220000 {
			compatible = "apple,s8000-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
			reg = <0x2 0x02220000 0 0x1000>;
			#performance-domain-cells = <0>;
		};

		serial0: serial@20a0c0000 {
			compatible = "apple,s5l-uart";
			reg = <0x2 0x0a0c0000 0x0 0x4000>;
			reg-io-width = <4>;
			interrupt-parent = <&aic>;
			interrupts = <AIC_IRQ 192 IRQ_TYPE_LEVEL_HIGH>;
			/* Use the bootloader-enabled clocks for now. */
			clocks = <&clkref>, <&clkref>;
			clock-names = "uart", "clk_uart_baud0";
			power-domains = <&ps_uart0>;
			status = "disabled";
		};

		pmgr: power-management@20e000000 {
			compatible = "apple,s8000-pmgr", "apple,pmgr", "syscon", "simple-mfd";
			#address-cells = <1>;
			#size-cells = <1>;

			reg = <0x2 0xe000000 0 0x8c000>;
		};

		aic: interrupt-controller@20e100000 {
			compatible = "apple,s8000-aic", "apple,aic";
			reg = <0x2 0x0e100000 0x0 0x100000>;
			#interrupt-cells = <3>;
			interrupt-controller;
			power-domains = <&ps_aic>;
		};

		dwi_bl: backlight@20e200080 {
			compatible = "apple,s8000-dwi-bl", "apple,dwi-bl";
			reg = <0x2 0x0e200080 0x0 0x8>;
			power-domains = <&ps_dwi>;
			status = "disabled";
		};

		pinctrl_ap: pinctrl@20f100000 {
			compatible = "apple,s8000-pinctrl", "apple,pinctrl";
			reg = <0x2 0x0f100000 0x0 0x100000>;
			power-domains = <&ps_gpio>;

			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pinctrl_ap 0 0 208>;
			apple,npins = <208>;

			interrupt-controller;
			#interrupt-cells = <2>;
			interrupt-parent = <&aic>;
			interrupts = <AIC_IRQ 42 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 43 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 44 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 45 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 46 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 47 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 48 IRQ_TYPE_LEVEL_HIGH>;
		};

		pinctrl_aop: pinctrl@2100f0000 {
			compatible = "apple,s8000-pinctrl", "apple,pinctrl";
			reg = <0x2 0x100f0000 0x0 0x100000>;
			power-domains = <&ps_aop_gpio>;

			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pinctrl_aop 0 0 42>;
			apple,npins = <42>;

			interrupt-controller;
			#interrupt-cells = <2>;
			interrupt-parent = <&aic>;
			interrupts = <AIC_IRQ 113 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 114 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 115 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 116 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 117 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 118 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 119 IRQ_TYPE_LEVEL_HIGH>;
		};

		pmgr_mini: power-management@210200000 {
			compatible = "apple,s8000-pmgr", "apple,pmgr", "syscon", "simple-mfd";
			#address-cells = <1>;
			#size-cells = <1>;

			reg = <0x2 0x10200000 0 0x84000>;
		};

		wdt: watchdog@2102b0000 {
			compatible = "apple,s8000-wdt", "apple,wdt";
			reg = <0x2 0x102b0000 0x0 0x4000>;
			clocks = <&clkref>;
			interrupt-parent = <&aic>;
			interrupts = <AIC_IRQ 4 IRQ_TYPE_LEVEL_HIGH>;
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupt-parent = <&aic>;
		interrupt-names = "phys", "virt";
		/* Note that A9 doesn't actually have a hypervisor (EL2 is not implemented). */
		interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>,
			     <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>;
	};
};

#include "s800-0-3-pmgr.dtsi"

/*
 * The A9 was made by two separate fabs on two different process
 * nodes: Samsung made the S8000 (APL0898) on 14nm and TSMC made
 * the S8003 (APL1022) on 16nm. There are some minor differences
 * such as timing in cpufreq state transistions.
 */