// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright 2025 Cix Technology Group Co., Ltd.
*
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/cix,sky1.h>
/ {
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "arm,cortex-a520";
enable-method = "psci";
reg = <0x0 0x0>;
device_type = "cpu";
capacity-dmips-mhz = <403>;
};
cpu1: cpu@100 {
compatible = "arm,cortex-a520";
enable-method = "psci";
reg = <0x0 0x100>;
device_type = "cpu";
capacity-dmips-mhz = <403>;
};
cpu2: cpu@200 {
compatible = "arm,cortex-a520";
enable-method = "psci";
reg = <0x0 0x200>;
device_type = "cpu";
capacity-dmips-mhz = <403>;
};
cpu3: cpu@300 {
compatible = "arm,cortex-a520";
enable-method = "psci";
reg = <0x0 0x300>;
device_type = "cpu";
capacity-dmips-mhz = <403>;
};
cpu4: cpu@400 {
compatible = "arm,cortex-a720";
enable-method = "psci";
reg = <0x0 0x400>;
device_type = "cpu";
capacity-dmips-mhz = <1024>;
};
cpu5: cpu@500 {
compatible = "arm,cortex-a720";
enable-method = "psci";
reg = <0x0 0x500>;
device_type = "cpu";
capacity-dmips-mhz = <1024>;
};
cpu6: cpu@600 {
compatible = "arm,cortex-a720";
enable-method = "psci";
reg = <0x0 0x600>;
device_type = "cpu";
capacity-dmips-mhz = <1024>;
};
cpu7: cpu@700 {
compatible = "arm,cortex-a720";
enable-method = "psci";
reg = <0x0 0x700>;
device_type = "cpu";
capacity-dmips-mhz = <1024>;
};
cpu8: cpu@800 {
compatible = "arm,cortex-a720";
enable-method = "psci";
reg = <0x0 0x800>;
device_type = "cpu";
capacity-dmips-mhz = <1024>;
};
cpu9: cpu@900 {
compatible = "arm,cortex-a720";
enable-method = "psci";
reg = <0x0 0x900>;
device_type = "cpu";
capacity-dmips-mhz = <1024>;
};
cpu10: cpu@a00 {
compatible = "arm,cortex-a720";
enable-method = "psci";
reg = <0x0 0xa00>;
device_type = "cpu";
capacity-dmips-mhz = <1024>;
};
cpu11: cpu@b00 {
compatible = "arm,cortex-a720";
enable-method = "psci";
reg = <0x0 0xb00>;
device_type = "cpu";
capacity-dmips-mhz = <1024>;
};
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
core2 {
cpu = <&cpu2>;
};
core3 {
cpu = <&cpu3>;
};
core4 {
cpu = <&cpu4>;
};
core5 {
cpu = <&cpu5>;
};
core6 {
cpu = <&cpu6>;
};
core7 {
cpu = <&cpu7>;
};
core8 {
cpu = <&cpu8>;
};
core9 {
cpu = <&cpu9>;
};
core10 {
cpu = <&cpu10>;
};
core11 {
cpu = <&cpu11>;
};
};
};
};
firmware {
ap_to_pm_scmi: scmi {
compatible = "arm,scmi";
mbox-names = "tx", "rx";
mboxes = <&mbox_ap2pm 8>, <&mbox_pm2ap 8>;
shmem = <&ap2pm_scmi_mem>, <&pm2ap_scmi_mem>;
#address-cells = <1>;
#size-cells = <0>;
scmi_clk: protocol@14 {
reg = <0x14>;
#clock-cells = <1>;
};
};
};
pmu-a520 {
compatible = "arm,cortex-a520-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_partition0>;
};
pmu-a720 {
compatible = "arm,cortex-a720-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_partition1>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
soc@0 {
compatible = "simple-bus";
ranges = <0 0 0 0 0x20 0>;
dma-ranges;
#address-cells = <2>;
#size-cells = <2>;
uart0: serial@40b0000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0x040b0000 0x0 0x1000>;
interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&scmi_clk CLK_TREE_FCH_UART0_FUNC>, <&scmi_clk CLK_TREE_FCH_UART0_APB>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
uart1: serial@40c0000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0x040c0000 0x0 0x1000>;
interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&scmi_clk CLK_TREE_FCH_UART1_FUNC>, <&scmi_clk CLK_TREE_FCH_UART1_APB>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
uart2: serial@40d0000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0x040d0000 0x0 0x1000>;
interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&scmi_clk CLK_TREE_FCH_UART2_FUNC>, <&scmi_clk CLK_TREE_FCH_UART2_APB>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
uart3: serial@40e0000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0x040e0000 0x0 0x1000>;
interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&scmi_clk CLK_TREE_FCH_UART3_FUNC>, <&scmi_clk CLK_TREE_FCH_UART3_APB>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
mbox_ap2se: mailbox@5060000 {
compatible = "cix,sky1-mbox";
reg = <0x0 0x05060000 0x0 0x10000>;
interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH 0>;
#mbox-cells = <1>;
cix,mbox-dir = "tx";
};
mbox_se2ap: mailbox@5070000 {
compatible = "cix,sky1-mbox";
reg = <0x0 0x05070000 0x0 0x10000>;
interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH 0>;
#mbox-cells = <1>;
cix,mbox-dir = "rx";
};
ap2pm_scmi_mem: shmem@6590000 {
compatible = "arm,scmi-shmem";
reg = <0x0 0x06590000 0x0 0x80>;
reg-io-width = <4>;
};
mbox_ap2pm: mailbox@6590080 {
compatible = "cix,sky1-mbox";
reg = <0x0 0x06590080 0x0 0xff80>;
interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 0>;
#mbox-cells = <1>;
cix,mbox-dir = "tx";
};
pm2ap_scmi_mem: shmem@65a0000 {
compatible = "arm,scmi-shmem";
reg = <0x0 0x065a0000 0x0 0x80>;
reg-io-width = <4>;
};
mbox_pm2ap: mailbox@65a0080 {
compatible = "cix,sky1-mbox";
reg = <0x0 0x065a0080 0x0 0xff80>;
interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH 0>;
#mbox-cells = <1>;
cix,mbox-dir = "rx";
};
mbox_sfh2ap: mailbox@8090000 {
compatible = "cix,sky1-mbox";
reg = <0x0 0x08090000 0x0 0x10000>;
interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;
#mbox-cells = <1>;
cix,mbox-dir = "rx";
};
mbox_ap2sfh: mailbox@80a0000 {
compatible = "cix,sky1-mbox";
reg = <0x0 0x080a0000 0x0 0x10000>;
interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;
#mbox-cells = <1>;
cix,mbox-dir = "tx";
};
gic: interrupt-controller@e010000 {
compatible = "arm,gic-v3";
reg = <0x0 0x0e010000 0 0x10000>, /* GICD */
<0x0 0x0e090000 0 0x300000>; /* GICR * 12 */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW 0>;
#interrupt-cells = <4>;
interrupt-controller;
#address-cells = <2>;
#size-cells = <2>;
ranges;
gic_its: msi-controller@e050000 {
compatible = "arm,gic-v3-its";
reg = <0x0 0x0e050000 0x0 0x30000>;
msi-controller;
#msi-cells = <1>;
};
ppi-partitions {
ppi_partition0: interrupt-partition-0 {
affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
};
ppi_partition1: interrupt-partition-1 {
affinity = <&cpu4 &cpu5 &cpu6 &cpu7 &cpu8 &cpu9 &cpu10 &cpu11>;
};
};
};
};
timer {
compatible = "arm,armv8-timer";
interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>,
<GIC_PPI 12 IRQ_TYPE_LEVEL_LOW 0>;
};
};
